Issued Patents 2022
Showing 26–50 of 70 patents
| Patent # | Title | Co-Inventors | Date |
|---|---|---|---|
| 11380589 | Selective removal of semiconductor fins | Veeraraghavan S. Basker, Ali Khakifirooz | 2022-07-05 |
| 11380842 | Phase change memory cell with second conductive layer | Juntao Li, Ruilong Xie, Junli Wang | 2022-07-05 |
| 11380778 | Vertical fin field effect transistor devices with self-aligned source and drain junctions | Juntao Li, Choonghyun Lee, Shogo Mochizuki | 2022-07-05 |
| 11378545 | Nanofluid sensor with real-time spatial sensing | Ali Khakifirooz, Ghavam G. Shahidi, Davood Shahrjerdi | 2022-07-05 |
| 11362093 | Co-integration of non-volatile memory on gate-all-around field effect transistor | Zhenxing Bi, Zheng Xu, Dexin Kong | 2022-06-14 |
| 11362194 | Transistor having confined source/drain regions with wrap-around source/drain contacts | Alexander Reznicek, Ruilong Xie, Marc A. Bergendahl | 2022-06-14 |
| 11362193 | Inverse T-shaped contact structures having air gap spacers | Choonghyun Lee, Juntao Li, Heng Wu, Peng Xu | 2022-06-14 |
| 11361928 | Piezoelectric vacuum transistor | Qing Cao, Zhengwen Li, Fei Liu | 2022-06-14 |
| 11355644 | Vertical field effect transistors with self aligned contacts | Yi Song, Juntao Li | 2022-06-07 |
| 11355588 | Strained and unstrained semiconductor device features formed on the same substrate | Juntao Li, Peng Xu | 2022-06-07 |
| 11355649 | Nanosheet transistor having abrupt junctions between the channel nanosheets and the source/drain extension regions | Choonghyun Lee, Juntao Li, Shogo Mochizuki | 2022-06-07 |
| 11349001 | Replacement gate cross-couple for static random-access memory scaling | Ruilong Xie, Carl Radens, Veeraraghavan S. Basker, Juntao Li | 2022-05-31 |
| 11342230 | Homogeneous densification of fill layers for controlled reveal of vertical fins | Choonghyun Lee, Juntao Li, Heng Wu, Peng Xu | 2022-05-24 |
| 11335773 | Trench contact resistance reduction | Zhenxing Bi, Juntao Li, Peng Xu | 2022-05-17 |
| 11329143 | Nanosheet transistors with thin inner spacers and tight pitch gate | Choonghyun Lee, Juntao Li, Peng Xu | 2022-05-10 |
| 11329001 | Embedded chip identification formed by directed self-assembly | Chi-Chun Liu | 2022-05-10 |
| 11322402 | Self-aligned top via scheme | Ruilong Xie, Chih-Chao Yang, Carl Radens, Juntao Li | 2022-05-03 |
| 11322588 | Contact source/drain resistance | Fee Li Lie, Choonghyun Lee, Hemanth Jagannathan, Oleg Gluschenkov | 2022-05-03 |
| 11315836 | Two-dimensional vertical fins | — | 2022-04-26 |
| 11316015 | Silicon germanium FinFET with low gate induced drain leakage current | Shogo Mochizuki, Choonghyun Lee, Juntao Li | 2022-04-26 |
| 11315799 | Back end of line structures with metal lines with alternating patterning and metallization schemes | Ruilong Xie, Chanro Park, Chih-Chao Yang, Juntao Li | 2022-04-26 |
| 11309397 | Contact over active gate employing a stacked spacer | — | 2022-04-19 |
| 11302799 | Method and structure for forming a vertical field-effect transistor | Peng Xu, Choonghyun Lee, Juntao Li | 2022-04-12 |
| 11296226 | Transistor having wrap-around source/drain contacts and under-contact spacers | Yi Song, Praveen Joseph, Andrew M. Greene | 2022-04-05 |
| 11295985 | Forming a backside ground or power plane in a stacked vertical transport field effect transistor | Chen Zhang, Tenko Yamashita, Lawrence A. Clevenger | 2022-04-05 |