| 11195792 |
Top via stack |
Brent A. Anderson, Lawrence A. Clevenger, Christopher J. Penny, Kisik Choi, Nicholas Anthony Lanzillo |
2021-12-07 |
| 11195795 |
Well-controlled edge-to-edge spacing between adjacent interconnects |
Brent A. Anderson, Lawrence A. Clevenger, Nicholas Anthony Lanzillo, Christopher J. Penny, Kisik Choi |
2021-12-07 |
| 11189568 |
Top via interconnect having a line with a reduced bottom dimension |
Brent A. Anderson, Lawrence A. Clevenger, Nicholas Anthony Lanzillo, Christopher J. Penny, Kisik Choi |
2021-11-30 |
| 11177166 |
Etch stop layer removal for capacitance reduction in damascene top via integration |
Christopher J. Penny, Brent A. Anderson, Lawrence A. Clevenger, Kisik Choi, Nicholas Anthony Lanzillo |
2021-11-16 |
| 11177160 |
Double patterned lithography using spacer assisted cuts for patterning steps |
Timothy Mathew Philip, Somnath Ghosh |
2021-11-16 |
| 11171084 |
Top via with next level line selective growth |
Brent A. Anderson, Lawrence A. Clevenger, Christopher J. Penny, Nicholas Anthony Lanzillo, Kisik Choi |
2021-11-09 |
| 11164777 |
Top via with damascene line and via |
Lawrence A. Clevenger, Brent A. Anderson, Kisik Choi, Nicholas Anthony Lanzillo, Christopher J. Penny |
2021-11-02 |
| 11158536 |
Patterning line cuts before line patterning using sacrificial fill material |
Daniel James Dechene, Timothy Mathew Philip, Somnath Ghosh |
2021-10-26 |
| 11158537 |
Top vias with subtractive line formation |
Brent A. Anderson, Lawrence A. Clevenger, Nicholas Anthony Lanzillo, Christopher J. Penny, Kisik Choi |
2021-10-26 |
| 11152464 |
Self-aligned isolation for nanosheet transistor |
Balasubramanian S. Pranatharthi Haran, Ruilong Xie, Veeraraghavan S. Basker |
2021-10-19 |
| 11152257 |
Barrier-less prefilled via formation |
Nicholas Anthony Lanzillo, Hosadurga Shobha, Junli Wang, Lawrence A. Clevenger, Christopher J. Penny +1 more |
2021-10-19 |
| 11152299 |
Hybrid selective dielectric deposition for aligned via integration |
Nicholas Anthony Lanzillo, Christopher J. Penny, Hosadurga Shobha, Lawrence A. Clevenger |
2021-10-19 |
| 11139201 |
Top via with hybrid metallization |
Koichi Motoyama, Nicholas Anthony Lanzillo, Christopher J. Penny, Somnath Ghosh, Lawrence A. Clevenger |
2021-10-05 |
| 11127815 |
Semiconductor device and method of forming the semiconductor device |
Marc A. Bergendahl, Gauri Karve, Fee Li Lie, Eric R. Miller, John R. Sporre +1 more |
2021-09-21 |
| 11062943 |
Top via interconnects with wrap around liner |
Koichi Motoyama, Nicholas Anthony Lanzillo, Christopher J. Penny, Somnath Ghosh, Lawrence A. Clevenger |
2021-07-13 |
| 11056391 |
Subtractive vFET process flow with replacement metal gate and metallic source/drain |
Hari V. Mallela, Reinaldo Vega, Rajasekhar Venigalla |
2021-07-06 |
| 11024709 |
Vertical fin field effect transistor with air gap spacers |
Hari V. Mallela, Reinaldo Vega, Rajasekhar Venigalla |
2021-06-01 |
| 10998193 |
Spacer-assisted lithographic double patterning |
Timothy Mathew Philip, Somnath Ghosh, Daniel James Dechene, Lawrence A. Clevenger |
2021-05-04 |
| 10978573 |
Spacer-confined epitaxial growth |
Karthik Yogendra, Ardasheir Rahman, Adra Carr |
2021-04-13 |
