Issued Patents 2021
Showing 1–10 of 10 patents
| Patent # | Title | Co-Inventors | Date |
|---|---|---|---|
| 11195923 | Method of fabricating a semiconductor device having reduced contact resistance | Gaurav Thareja, Xuebin Li, Abhishek Dube, Yi-Chiau Huang, Tushar Mandrekar +3 more | 2021-12-07 |
| 11189635 | 3D-NAND mold | Chang-Seok Kang, Tomohiko Kitajima, Mukund Srinivasan | 2021-11-30 |
| 11177254 | Stacked transistor device | Suketu Arun Parikh | 2021-11-16 |
| 11171141 | Gap fill methods of forming buried word lines in DRAM without forming bottom voids | Priyadarshi Panda, Seshadri Ganguli, Sang Ho Yu, Sung-Kwan Kang, Gill Yong Lee +2 more | 2021-11-09 |
| 11164938 | DRAM capacitor module | Uday Mitra, Regina Freed, Ho-yung David Hwang, Lequn Liu | 2021-11-02 |
| 11152479 | Semiconductor device, method of making a semiconductor device, and processing system | Gaurav Thareja, Xuebin Li, Abhishek Dube, Yi-Chiau Huang, Andy Lo +2 more | 2021-10-19 |
| 11114320 | Processing system and method of forming a contact | Gaurav Thareja, Takashi Kuratomi, Avgerinos V. Gelatos, Xianmin Tang, Keyvan Kashefizadeh +3 more | 2021-09-07 |
| 11004687 | Gate contact over active processes | Gaurav Thareja, Keyvan Kashefizadeh, Xikun Wang, Anchuan Wang, Sean M. Seutter +1 more | 2021-05-11 |
| 10903112 | Methods and apparatus for smoothing dynamic random access memory bit line metal | Priyadarshi Panda, Jianxin Lei, In-Seok Hwang, Nobuyuki Sasaki | 2021-01-26 |
| 10892187 | Method for creating a fully self-aligned via | Regina Freed, Uday Mitra | 2021-01-12 |