JD

Javier A. Delacruz

XC Xcelsis: 17 patents #1 of 16Top 7%
IT Invensas Bonding Technologies: 8 patents #2 of 14Top 15%
IN Invensas: 4 patents #8 of 37Top 25%
📍 San Jose, CA: #18 of 6,906 inventorsTop 1%
🗺 California: #159 of 68,989 inventorsTop 1%
Overall (2020): #949 of 565,922Top 1%
29
Patents 2020

Issued Patents 2020

Showing 1–25 of 29 patents

Patent #TitleCo-InventorsDate
10879210 Bonded structures Paul M. Enquist, Liang Wang, Rajesh Katkar, Arkalgud R. Sitaram 2020-12-29
10879207 Bonded structures Liang Wang, Rajesh Katkar, Arkalgud R. Sitaram 2020-12-29
10832912 Direct-bonded native interconnects and active base die Steven Teig, Shaowu Huang, William C. Plants, David Edward Fisch 2020-11-10
10790222 Bonding of laminates with electrical interconnects Belgacem Haba, Wael Zohni, Liang Wang, Akash Agrawal 2020-09-29
10784191 Interface structures and methods for forming same Shaowu Huang, Belgacem Haba 2020-09-22
10748824 Probe methodology for ultrafine pitch interconnects Paul M. Enquist, Gaius Gillman Fountain, Jr., Ilyas Mohammed 2020-08-18
10719762 Three dimensional chip structure implementing machine trained network Steven Teig, Kenneth Duong 2020-07-21
10700094 Device disaggregation for improved performance Don Draper, Jung Ko, Steven Teig 2020-06-30
10684929 Self healing compute array Steven Teig, David Edward Fisch, William C. Plants 2020-06-16
10672744 3D compute circuit with high density Z-axis interconnects Steven Teig, Ilyas Mohammed, Kenneth Duong 2020-06-02
10672743 3D Compute circuit with high density z-axis interconnects Steven Teig, Ilyas Mohammed, Kenneth Duong 2020-06-02
10672745 3D processor Steven Teig, Ilyas Mohammed, Kenneth Duong 2020-06-02
10672663 3D chip sharing power circuit Steven Teig, Ilyas Mohammed, Eric Nequist 2020-06-02
10664564 Systems and methods for inter-die block level design Eric Nequist, Jung Ko, Kenneth Duong 2020-05-26
10658313 Selective recess Rajesh Katkar, Shaowu Huang, Gaius Gillman Fountain, Jr., Liang Wang, Laura Wills Mirkarimi 2020-05-19
10658302 Wire bonding method and apparatus for electromagnetic interference shielding Shaowu Huang 2020-05-19
10607937 Increased contact alignment tolerance for direct bonding Paul M. Enquist, Gaius Gillman Fountain, Jr. 2020-03-31
10607136 Time borrowing between layers of a three dimensional chip stack Steven Teig, Kenneth Duong 2020-03-31
10600691 3D chip sharing power interconnect layer Steven Teig, Ilyas Mohammed 2020-03-24
10600780 3D chip sharing data bus circuit Steven Teig, Ilyas Mohammed 2020-03-24
10600747 Vertical capacitors for microelectronics Belgacem Haba 2020-03-24
10600735 3D chip sharing data bus Steven Teig, Ilyas Mohammed 2020-03-24
10593651 Systems and methods for flash stacking Belgacem Haba, Ilyas Mohammed 2020-03-17
10593667 3D chip with shielded clock lines Steven Teig, Ilyas Mohammed 2020-03-17
10586786 3D chip sharing clock interconnect layer Steven Teig, Ilyas Mohammed, Eric Nequist 2020-03-10