Issued Patents 2020
Showing 1–24 of 24 patents
| Patent # | Title | Co-Inventors | Date |
|---|---|---|---|
| 10871578 | Differential correction map for GNSS | Brian W. Kroeger, Paul J. Peyla | 2020-12-22 |
| 10867247 | Machine learning through multiple layers of novel machine trained processing nodes | — | 2020-12-15 |
| 10832912 | Direct-bonded native interconnects and active base die | Javier A. Delacruz, Shaowu Huang, William C. Plants, David Edward Fisch | 2020-11-10 |
| 10762420 | Self repairing neural network | Kenneth Duong | 2020-09-01 |
| 10742959 | Use of machine-trained network for misalignment-insensitive depth perception | Andrew C. Mihal | 2020-08-11 |
| 10740434 | Reduced dot product computation circuit | Kenneth Duong, Jung Ko | 2020-08-11 |
| 10719762 | Three dimensional chip structure implementing machine trained network | Kenneth Duong, Javier A. Delacruz | 2020-07-21 |
| 10700094 | Device disaggregation for improved performance | Javier A. Delacruz, Don Draper, Jung Ko | 2020-06-30 |
| 10684929 | Self healing compute array | Javier A. Delacruz, David Edward Fisch, William C. Plants | 2020-06-16 |
| 10672743 | 3D Compute circuit with high density z-axis interconnects | Ilyas Mohammed, Kenneth Duong, Javier A. Delacruz | 2020-06-02 |
| 10671888 | Using batches of training items for training a network | Eric A. Sather, Andrew C. Mihal | 2020-06-02 |
| 10672663 | 3D chip sharing power circuit | Javier A. Delacruz, Ilyas Mohammed, Eric Nequist | 2020-06-02 |
| 10672744 | 3D compute circuit with high density Z-axis interconnects | Ilyas Mohammed, Kenneth Duong, Javier A. Delacruz | 2020-06-02 |
| 10672745 | 3D processor | Ilyas Mohammed, Kenneth Duong, Javier A. Delacruz | 2020-06-02 |
| 10607136 | Time borrowing between layers of a three dimensional chip stack | Kenneth Duong, Javier A. Delacruz | 2020-03-31 |
| 10600780 | 3D chip sharing data bus circuit | Javier A. Delacruz, Ilyas Mohammed | 2020-03-24 |
| 10600735 | 3D chip sharing data bus | Javier A. Delacruz, Ilyas Mohammed | 2020-03-24 |
| 10600691 | 3D chip sharing power interconnect layer | Javier A. Delacruz, Ilyas Mohammed | 2020-03-24 |
| 10592732 | Probabilistic loss function for training network with triplets | Eric A. Sather, Andrew C. Mihal | 2020-03-17 |
| 10593667 | 3D chip with shielded clock lines | Javier A. Delacruz, Ilyas Mohammed | 2020-03-17 |
| 10586151 | Mitigating overfitting in training machine trained networks | — | 2020-03-10 |
| 10586786 | 3D chip sharing clock interconnect layer | Javier A. Delacruz, Ilyas Mohammed, Eric Nequist | 2020-03-10 |
| 10580735 | Stacked IC structure with system level wiring on multiple sides of the IC die | Ilyas Mohammed, Javier A. Delacruz | 2020-03-03 |
| 10580757 | Face-to-face mounted IC dies with orthogonal top interconnect layers | Eric Nequist, Javier A. Delacruz, Ilyas Mohammed, Laura Mirkarimi | 2020-03-03 |