Patent Leaderboard
USPTO Patent Rankings Data through Sept 30, 2025
AM

Anand S. Murthy

Intel: 31 patents #19 of 5,492Top 1%
Sony: 1 patents #1,372 of 3,167Top 45%
Portland, OR: #9 of 1,857 inventorsTop 1%
Oregon: #16 of 4,557 inventorsTop 1%
Overall (2020): #800 of 565,922Top 1%
32 Patents 2020

Issued Patents 2020

Showing 1–25 of 32 patents

Patent #TitleCo-InventorsDate
10879365 Transistors with non-vertical gates Cheng-Ying Huang, Sean T. Ma, Willy Rachmady, Gilbert Dewey, Matthew V. Metz +3 more 2020-12-29
10879353 Selective germanium P-contact metalization through trench Glenn A. Glass, Tahir Ghani 2020-12-29
10879241 Techniques for controlling transistor sub-fin leakage Glenn A. Glass, Prashant Majhi, Tahir Ghani, Daniel B. Aubertine, Heidi M. Meyer +2 more 2020-12-29
10854752 High mobility strained channels for fin-based NMOS transistors Stephen M. Cea, Roza Kotlyar, Harold W. Kennel, Glenn A. Glass, Willy Rachmady +1 more 2020-12-01
10818793 Indium-rich NMOS transistor channels Chandra S. Mohapatra, Glenn A. Glass, Tahir Ghani, Willy Rachmady, Jack T. Kavalieros +3 more 2020-10-27
10811496 Transistor devices having source/drain structure configured with high germanium content portion Glenn A. Glass 2020-10-20
10804357 Integration methods to fabricate internal spacers for nanowire devices Seiyon Kim, Kelin J. Kuhn, Tahir Ghani, Mark Armstrong, Rafael Rios +2 more 2020-10-13
10797150 Differential work function between gate stack metals to reduce parasitic capacitance Sean T. Ma, Willy Rachmady, Matthew V. Metz, Chandra S. Mohapatra, Gilbert Dewey +3 more 2020-10-06
10770593 Beaded fin transistor Gilbert Dewey, Tahir Ghani, Willy Rachmady, Jack T. Kavalieros, Matthew V. Metz +1 more 2020-09-08
10755984 Replacement channel etch for high quality interface Glenn A. Glass, Ying-Feng PANG, Nabil G. Mistkawi, Tahir Ghani, Huang-Lin Chao 2020-08-25
10749032 Techniques for forming transistors including group III-V material nanowires using sacrificial group IV material layers Chandra S. Mohapatra, Glenn A. Glass, Karthik Jambunathan, Willy Rachmady, Gilbert Dewey +2 more 2020-08-18
10748900 Fin-based III-V/SI or GE CMOS SAGE integration Willy Rachmady, Matthew V. Metz, Gilbert Dewey, Chandra S. Mohapatra, Jack T. Kavalieros +1 more 2020-08-18
10734412 Backside contact resistance reduction for semiconductor devices with metallization on both sides Glenn A. Glass, Karthik Jambunathan, Chandra S. Mohapatra, Mauro J. Kobrinsky, Patrick Morrow 2020-08-04
10700178 Contact resistance reduction employing germanium overlayer pre-contact metalization Glenn A. Glass, Tahir Ghani 2020-06-30
10692973 Germanium-rich channel transistors including one or more dopant diffusion barrier elements Glenn A. Glass, Karthik Jambunathan, Benjamin Chu-Kung, Seung Hoon Sung, Jack T. Kavalieros +2 more 2020-06-23
10692974 Deuterium-based passivation of non-planar transistor interfaces Prashant Majhi, Glenn A. Glass, Tahir Ghani, Aravind S. Killampalli, Mark R. Brazier +1 more 2020-06-23
10672868 Methods of forming self aligned spacers for nanowire device structures Karthik Jambunathan, Glenn A. Glass, Jun Sung Kang, Seiyon Kim 2020-06-02
10651288 Pseudomorphic InGaAs on GaAs for gate-all-around transistors Chandra S. Mohapatra, Glenn A. Glass, Willy Rachmady, Gilbert Dewey, Jack T. Kavalieros +2 more 2020-05-12
10644137 III-V finfet transistor with V-groove S/D profile for improved access resistance Willy Rachmady, Matthew V. Metz, Gilbert Dewey, Sean T. Ma, Chandra S. Mohapatra +3 more 2020-05-05
10644112 Systems, methods and devices for isolation for subfin leakage Benjamin Chu-Kung, Van H. Le, Seung Hoon Sung, Jack T. Kavalieros, Ashish Agrawal +5 more 2020-05-05
10636912 FINFET transistor having a tapered subfin structure Gilbert Dewey, Willy Rachmady, Matthew V. Metz, Jack T. Kavalieros, Chandra S. Mohapatra +2 more 2020-04-28
10586848 Apparatus and methods to create an active channel having indium rich side and bottom surfaces Chandra S. Mohapatra, Glenn A. Glass, Matthew V. Metz, Willy Rachmady, Gilbert Dewey +2 more 2020-03-10
10580860 Integration methods to fabricate internal spacers for nanowire devices Seiyon Kim, Kelin J. Kuhn, Tahir Ghani, Mark Armstrong, Rafael Rios +2 more 2020-03-03
10580865 Transistor with a sub-fin dielectric region under a gate Willy Rachmady, Matthew V. Metz, Gilbert Dewey, Chandra S. Mohapatra, Nadia M. Rahhal-Orabi +2 more 2020-03-03
10573750 Methods of forming doped source/drain contacts and structures formed thereby Glenn A. Glass, Karthik Jambunathan, Chandra S. Mohapatra, Seiyon Kim 2020-02-25