{"@context": "https://schema.org", "@type": "BreadcrumbList", "itemListElement": [{"@type": "ListItem", "position": 1, "name": "Home", "item": "https://www.patentleaderboard.com/"}, {"@type": "ListItem", "position": 2, "name": "2020", "item": "https://www.patentleaderboard.com/2020/"}, {"@type": "ListItem", "position": 3, "name": "Intel", "item": "https://www.patentleaderboard.com/2020/company/intel"}, {"@type": "ListItem", "position": 4, "name": "Heidi M. Meyer", "item": "https://www.patentleaderboard.com/2020/inventor/fl:he_ln:meyer-6"}]}

Home › 2020 › Intel › Heidi M. Meyer

Heidi M. Meyer — 1 Patent in 2020

Intel: 1 patents #2,160 of 5,492Top 40%

Hillsboro, OR: #223 of 521 inventorsTop 45%

Oregon: #1,921 of 4,557 inventorsTop 45%

Overall (2020): #452,436 of 565,922Top 80%

1 Patents 2020

Issued Patents 2020

Showing 1–1 of 1 patents

Patent #	Title	Co-Inventors	Date	Approx Value ⓘ
10879241	Techniques for controlling transistor sub-fin leakage	Glenn A. Glass, Prashant Majhi, Anand S. Murthy, Tahir Ghani, Daniel B. Aubertine +2 more	2020-12-29	$24,597,000

Heidi M. Meyer — 1 Patent in 2020

Issued Patents 2020

Patent Widget