| 10522410 |
Performing concurrent diffusion break, gate and source/drain contact cut etch processes |
Laertis Economikos, Hui Zang, Ruilong Xie, Hong Yu |
2019-12-31 |
| 10522644 |
Different upper and lower spacers for contact |
Guowei Xu, Hui Zang, Scott Beasor |
2019-12-31 |
| 10522538 |
Using source/drain contact cap during gate cut |
Shesh Mani Pandey, Jiehui Shu, Laertis Economikos, Hui Zang, Ruilong Xie +2 more |
2019-12-31 |
| 10475890 |
Scaled memory structures or other logic devices with middle of the line cuts |
Wei Zhao, Hui Zang, Hong Yu, Zhenyu Hu, Scott Beasor +3 more |
2019-11-12 |
| 10468481 |
Self-aligned single diffusion break isolation with reduction of strain loss |
Hui Zang, Chun Yu Wong, Kwan-Yong Lim |
2019-11-05 |
| 10431499 |
Insulating gate separation structure |
Guowei Xu, Hui Zang, Yue Zhong |
2019-10-01 |
| 10403742 |
Field-effect transistors with fins formed by a damascene-like process |
Wei Zhao, David Paul Brunco, Jiehui Shu, Shesh Mani Pandey, Jinping Liu +1 more |
2019-09-03 |
| 10396206 |
Gate cut method |
Ashish Jha, Wei Hong, Wei Zhao, Tae Jeong LEE, Zhenyu Hu |
2019-08-27 |
| 10388652 |
Intergrated circuit structure including single diffusion break abutting end isolation region, and methods of forming same |
Yongiun Shi, Lei Sun, Laertis Economikos, Ruilong Xie, Lars Liebmann +4 more |
2019-08-20 |
| 10373877 |
Methods of forming source/drain contact structures on integrated circuit products |
Hong Yu, Hui Zang, Wei Zhao, Yue Zhong, Guowei Xu +3 more |
2019-08-06 |
| 10373875 |
Contacts formed with self-aligned cuts |
Ruilong Xie, Daniel Jaeger, Chanro Park, Laertis Economikos, Hui Zang |
2019-08-06 |
| 10361289 |
Gate oxide formation through hybrid methods of thermal and deposition processes and method for producing the same |
Wei Zhao, Shahab Siddiqui, Ting-Hsiang Hung, Yiheng Xu, Beth Baumert +4 more |
2019-07-23 |
| 10325811 |
Field-effect transistors with fins having independently-dimensioned sections |
David Paul Brunco, Wei Zhao |
2019-06-18 |
| 10249616 |
Methods of forming a resistor structure between adjacent transistor gates on an integrated circuit product and the resulting devices |
Hui Zang, Manfred Eller, Daniel Jaeger |
2019-04-02 |
| 10192746 |
STI inner spacer to mitigate SDB loading |
Ashish Jha, Hui Zhan, Hong Yu, Zhenyu Hu, Edward Reis +1 more |
2019-01-29 |
