Issued Patents 2003
Showing 1–17 of 17 patents
| Patent # | Title | Co-Inventors | Date |
|---|---|---|---|
| 6657284 | Graded dielectric layer and method for fabrication thereof | Lain-Jong Li, Shwang-Ming Jeng, Chen-Hua Yu | 2003-12-02 |
| 6654109 | System for detecting surface defects in semiconductor wafers | Lain-Jong Li, Chung-Chi Ko | 2003-11-25 |
| 6638328 | Bimodal slurry system | Shen-Nan Lee, Tsu Shih | 2003-10-28 |
| 6635211 | Reinforced polishing pad for linear chemical mechanical polishing and method for forming | Wen-Chih Chiou, Ying-Ho Chen, Tsu Shih | 2003-10-21 |
| 6634930 | Method and apparatus for preventing metal corrosion during chemical mechanical polishing | Ying-Ho Chen, Wen-Chih Chiou, Tsu Shih, Chia-Ming Yang | 2003-10-21 |
| 6623654 | Thin interface layer to improve copper etch stop | Bi-Trong Chen, Lain-Jong Li, Shu E Ku, Tien-I Bao, Lih-Ping Li | 2003-09-23 |
| 6620725 | Reduction of Cu line damage by two-step CMP | Shau-Lin Shue, Ming-Hsing Tsai, Wen-Jye Tsai, Ying-Ho Chen, Tsu Shih +1 more | 2003-09-16 |
| 6620034 | Way to remove Cu line damage after Cu CMP | Tsu Shih, Jih-Churng Jwu, Ying-Ho Chen | 2003-09-16 |
| 6599847 | Sandwich composite dielectric layer yielding improved integrated circuit device reliability | Chen-Hua Yu | 2003-07-29 |
| 6589872 | Use of low-high slurry flow to eliminate copper line damages | Jih-Churng Twu, Ying-Ho Chen, Tsu Shih | 2003-07-08 |
| 6559040 | Process for polishing the top surface of a polysilicon gate | Chen-Hua Yu, Chung-Long Chang | 2003-05-06 |
| 6544891 | Method to eliminate post-CMP copper flake defect | Ying-Ho Chen, Wen-Chih Chiou, Tsu Shih | 2003-04-08 |
| 6541382 | Lining and corner rounding method for shallow trench isolation | Juing-Yi Cheng | 2003-04-01 |
| 6524906 | Chemical mechanical polishing of polysilicon plug using a silicon nitride stop layer | Chung-Long Chang | 2003-02-25 |
| 6518183 | Hillock inhibiting method for forming a passivated copper containing conductor layer | Weng Chang, Tien-I Bao, Ying-Ho Chen | 2003-02-11 |
| 6511887 | Method for making FET gate oxides with different thicknesses using a thin silicon nitride layer and a single oxidation step | Mo Yu | 2003-01-28 |
| 6503818 | Delamination resistant multi-layer composite dielectric layer employing low dielectric constant dielectric material | — | 2003-01-07 |