Issued Patents All Time
Showing 101–120 of 120 patents
| Patent # | Title | Co-Inventors | Date |
|---|---|---|---|
| 9779952 | Method for laterally trimming a hardmask | Sergey Voronin | 2017-10-03 |
| 9768033 | Methods for high precision etching of substrates | Mingmei Wang, Peter L. G. Ventzek | 2017-09-19 |
| 9666447 | Method for selectivity enhancement during dry plasma etching | Vinayak Rastogi | 2017-05-30 |
| 9607843 | Method for roughness improvement and selectivity enhancement during arc layer etch via adjustment of carbon-fluorine content | Vinayak Rastogi | 2017-03-28 |
| 9576816 | Method for roughness improvement and selectivity enhancement during arc layer etch using hydrogen | Vinayak Rastogi | 2017-02-21 |
| 9570313 | Method for etching high-K dielectric using pulsed bias power | Akiteru Ko | 2017-02-14 |
| 9530626 | Method and apparatus for ESC charge control for wafer clamping | Jason Marion, Sonam D. Sherpa, Sergey Voronin, Yoshio Ishikawa, Takashi Enomoto | 2016-12-27 |
| 9530667 | Method for roughness improvement and selectivity enhancement during arc layer etch using carbon | Vinayak Rastogi | 2016-12-27 |
| 9378975 | Etching method to form spacers having multiple film layers | Blake Parkinson | 2016-06-28 |
| 9318343 | Method to improve etch selectivity during silicon nitride spacer etch | Blake Parkinson | 2016-04-19 |
| 9159575 | Method for etching high-K dielectric using pulsed bias power | Akiteru Ko | 2015-10-13 |
| 9155183 | Adjustable slot antenna for control of uniformity in a surface wave plasma source | Sergey Voronin | 2015-10-06 |
| 9111746 | Method for reducing damage to low-k gate spacer during etching | Angelique Raley | 2015-08-18 |
| 9101042 | Control of uniformity in a surface wave plasma source | Sergey Voronin | 2015-08-04 |
| 9054050 | Method for deep silicon etching using gas pulsing | Scott Lefevre | 2015-06-09 |
| 8906760 | Aspect ratio dependent deposition to improve gate spacer profile, fin-loss and hardmask-loss for FinFET scheme | Angelique Raley | 2014-12-09 |
| 8809194 | Formation of SiOCl-containing layer on spacer sidewalls to prevent CD loss during spacer etch | Kaushik A. Kumar | 2014-08-19 |
| 8735291 | Method for etching high-k dielectric using pulsed bias power | Akiteru Ko | 2014-05-27 |
| 8592327 | Formation of SiOCl-containing layer on exposed low-k surfaces to reduce low-k damage | Kaushik A. Kumar | 2013-11-26 |
| 8551877 | Sidewall and chamfer protection during hard mask removal for interconnect patterning | Kaushik A. Kumar | 2013-10-08 |