Issued Patents All Time
Showing 101–125 of 167 patents
| Patent # | Title | Co-Inventors | Date |
|---|---|---|---|
| 9064699 | Methods of forming semiconductor patterns including reduced dislocation defects and devices formed using such methods | Wei-E Wang, Robert C. Bowen | 2015-06-23 |
| 8927373 | Methods of fabricating non-planar transistors including current enhancing structures | Kang-ill Seo | 2015-01-06 |
| 8828818 | Methods of fabricating integrated circuit device with fin transistors having different threshold voltages | — | 2014-09-09 |
| 7560779 | Method for forming a mixed voltage circuit having complementary devices | Jarvis Benjamin Jacobs | 2009-07-14 |
| 7459734 | Method for manufacturing and structure for transistors with reduced gate to contact spacing | Keith A. Joyner | 2008-12-02 |
| 7443007 | Trench isolation structure having an implanted buffer layer | Rick L. Wise | 2008-10-28 |
| D571642 | Reversible asymmetric hanger for suspending objects such as wires, strips and loops | — | 2008-06-24 |
| 7371658 | Trench isolation structure and a method of manufacture therefor | Rick L. Wise | 2008-05-13 |
| D563210 | Asymmetric hanger for the suspension of objects | — | 2008-03-04 |
| D556028 | Reversible asymmetric hanger for suspension of objects by means including wires, strips and loops | — | 2007-11-27 |
| 7163878 | Ultra-shallow arsenic junction formation in silicon germanium | Puneet Kohli, Rick L. Wise, Amitabh Jain | 2007-01-16 |
| 7160782 | Method of manufacture for a trench isolation structure having an implanted buffer layer | Rick L. Wise | 2007-01-09 |
| 6767777 | Method for manufacturing and structure for transistors with reduced gate to contact spacing including etching to thin the spacers | Keith A. Joyner | 2004-07-27 |
| 6723616 | Process of increasing screen dielectric thickness | Seetharaman Sridhar, Youngmin Kim, Zhiqiang Wu | 2004-04-20 |
| 6686300 | Sub-critical-dimension integrated circuit features | Manoj Mehrotra, John N. Randall | 2004-02-03 |
| 6660595 | Implantation method for simultaneously implanting in one region and blocking the implant in another region | — | 2003-12-09 |
| 6635584 | Versatile system for forming uniform wafer surfaces | Zhiqiang Wu, Manoj Mehrotra | 2003-10-21 |
| 6583013 | Method for forming a mixed voltage circuit having complementary devices | Jarvis Benjamin Jacobs | 2003-06-24 |
| 6579770 | Sidewall process and method of implantation for improved CMOS with benefit of low CGD, improved doping profiles, and insensitivity to chemical processing | Mahalingam Nandakumar | 2003-06-17 |
| 6461928 | Methodology for high-performance, high reliability input/output devices and analog-compatible input/output and core devices using core device implants | — | 2002-10-08 |
| 6413824 | METHOD TO PARTIALLY OR COMPLETELY SUPPRESS POCKET IMPLANT IN SELECTIVE CIRCUIT ELEMENTS WITH NO ADDITIONAL MASK IN A CMOS FLOW WHERE SEPARATE MASKING STEPS ARE USED FOR THE DRAIN EXTENSION IMPLANTS FOR THE LOW VOLTAGE AND HIGH VOLTAGE TRANSISTORS | Amitava Chatterjee, Alec J. Morton, Taylor R. Efland, Chin-Yu Tsai, James R. Hellums | 2002-07-02 |
| 6352900 | Controlled oxide growth over polysilicon gates for improved transistor characteristics | Manoj Mehrotra, Jerry Hu, Amitava Chatterjee | 2002-03-05 |
| 6346447 | Shallow-implant elevated source/drain doping from a sidewall dopant source | — | 2002-02-12 |
| 6329225 | Tight pitch gate devices with enlarged contact areas for deep source and drain terminals and method | — | 2001-12-11 |
| 6326289 | Method of forming a silicide layer using a pre-amorphization implant which is blocked from source/drain regions by a layer of photoresist | Jorge A. Kittl | 2001-12-04 |