Issued Patents All Time
Showing 76–100 of 167 patents
| Patent # | Title | Co-Inventors | Date |
|---|---|---|---|
| 9691860 | Methods of forming defect-free SRB onto lattice-mismatched substrates and defect-free fins on insulators | Wei-E Wang, Rwik Sengupta | 2017-06-27 |
| 9685564 | Gate-all-around field effect transistors with horizontal nanosheet conductive channel structures for MOL/inter-channel spacing and related cell architectures | Rwik Sengupta, Joon Goo Hong, Titash Rakshit | 2017-06-20 |
| 9685509 | Finfet devices including high mobility channel materials with materials of graded composition in recessed source/drain regions | Jorge A. Kittl, Robert C. Bowen | 2017-06-20 |
| 9653287 | S/D connection to individual channel layers in a nanosheet FET | Joon Goo Hong, Jorge A. Kittl, Borna J. Obradovic | 2017-05-16 |
| 9647098 | Thermionically-overdriven tunnel FETs and methods of fabricating the same | Borna J. Obradovic, Robert C. Bowen, Dharmendar Reddy Palle | 2017-05-09 |
| 9634140 | Fabricating metal source-drain stressor in a MOS device channel | Jorge A. Kittl, Ganesh Hegde | 2017-04-25 |
| 9613907 | Low resistivity damascene interconnect | Ganesh Hegde, Jorge A. Kittl, Robert C. Bowen | 2017-04-04 |
| 9601586 | Methods of forming semiconductor devices, including forming a metal layer on source/drain regions | Jorge A. Kittl, Joon Goo Hong | 2017-03-21 |
| 9583590 | Integrated circuit devices including FinFETs and methods of forming the same | Borna J. Obradovic, Robert C. Bowen | 2017-02-28 |
| 9570395 | Semiconductor device having buried power rail | Rwik Sengupta, Joon Goo Hong | 2017-02-14 |
| 9570609 | Crystalline multiple-nanosheet strained channel FETs and methods of fabricating the same | Borna J. Obradovic, Robert C. Bowen | 2017-02-14 |
| 9525053 | Integrated circuit devices including strained channel regions and methods of forming the same | Ryan M. Hatcher, Robert C. Bowen, Jorge A. Kittl | 2016-12-20 |
| 9490323 | Nanosheet FETs with stacked nanosheets having smaller horizontal spacing than vertical spacing for large effective width | Borna J. Obradovic, Rwik Sengupta | 2016-11-08 |
| 9466669 | Multiple channel length finFETs with same physical gate length | Borna J. Obradovic, Rwik Sengupta | 2016-10-11 |
| 9461114 | Semiconductor devices with structures for suppression of parasitic bipolar effect in stacked nanosheet FETs and methods of fabricating the same | Borna J. Obradovic, Ryan M. Hatcher, Robert C. Bowen | 2016-10-04 |
| 9431492 | Integrated circuit devices including contacts and methods of forming the same | Jorge A. Kittl, Dharmendar Reddy Palle | 2016-08-30 |
| 9425275 | Integrated circuit chips having field effect transistors with different gate designs | Dharmendar Reddy Palle, Borna J. Obradovic | 2016-08-23 |
| 9406508 | Methods of forming a semiconductor layer including germanium with low defectivity | Jorge A. Kittl | 2016-08-02 |
| 9343303 | Methods of forming low-defect strain-relaxed layers on lattice-mismatched substrates and related semiconductor structures and devices | Wei-E Wang | 2016-05-17 |
| 9331176 | Methods of forming field effect transistors, including forming source and drain regions in recesses of semiconductor fins | Dong Won Kim | 2016-05-03 |
| 9287357 | Integrated circuits with Si and non-Si nanosheet FET co-integration with low band-to-band tunneling and methods of fabricating the same | Borna J. Obradovic, Rwik Sengupta, Dharmendar Reddy Palle, Robert C. Bowen | 2016-03-15 |
| 9263549 | Fin-FET transistor with punchthrough barrier and leakage protection regions | Chris Bowen | 2016-02-16 |
| 9257327 | Methods of forming a Field Effect Transistor, including forming a region providing enhanced oxidation | Kang-ill Seo | 2016-02-09 |
| 9236444 | Methods of fabricating quantum well field effect transistors having multiple delta doped layers | Robert C. Bowen | 2016-01-12 |
| 9178045 | Integrated circuit devices including FinFETS and methods of forming the same | Borna J. Obradovic, Robert C. Bowen | 2015-11-03 |