Issued Patents All Time
Showing 26–50 of 167 patents
| Patent # | Title | Co-Inventors | Date |
|---|---|---|---|
| 10868193 | Nanosheet field effect transistor cell architecture | Rwik Sengupta, Joon Goo Hong, Titash Rakshit | 2020-12-15 |
| 10860923 | High-density neuromorphic computing element | Borna J. Obradovic, Titash Rakshit | 2020-12-08 |
| 10861950 | Integrated circuit including field effect transistors having a contact on active gate compatible with a small cell area having a small contacted poly pitch | Rwik Sengupta, Joon Goo Hong, Titash Rakshit | 2020-12-08 |
| 10854591 | Semiconductor device including a repeater/buffer at upper metal routing layers and methods of manufacturing the same | Wei-E Wang, Titash Rakshit, Borna J. Obradovic, Chris Bowen | 2020-12-01 |
| 10825723 | Semiconductor device and method for making the same | Joon Goo Hong, Harsono S. Simka | 2020-11-03 |
| 10811415 | Semiconductor device and method for making the same | Rwik Sengupta, Joon Goo Hong, Vassilios Gerousis | 2020-10-20 |
| 10784198 | Power rail for standard cell block | Rwik Sengupta, Andrew Paul Hoover, Matthew Berzins, Sam Tower | 2020-09-22 |
| 10700068 | Field effect transistor with decoupled channel and methods of manufacturing the same | Borna J. Obradovic | 2020-06-30 |
| 10586738 | Method of providing source and drain doping for CMOS architecture including FinFET and semiconductor devices so formed | Wei-E Wang, Borna J. Obradovic, Joon Goo Hong | 2020-03-10 |
| 10566330 | Dielectric separation of partial GAA FETs | Borna J. Obradovic, Dharmendar Reddy Palle, Rwik Sengupta, Mohammad Ali Pourghaderi | 2020-02-18 |
| 10510665 | Low-k dielectric pore sealant and metal-diffusion barrier formed by doping and method for forming the same | Ganesh Hegde, Jorge A. Kittl, Chris Bowen | 2019-12-17 |
| 10475930 | Method of forming crystalline oxides on III-V materials | Wei-E Wang, Robert M. Wallace, Xiaoye Qin | 2019-11-12 |
| 10446400 | Method of forming multi-threshold voltage devices and devices so formed | Wei-E Wang, Borna J. Obradovic | 2019-10-15 |
| 10424581 | Sub 59 MV/decade SI CMOS compatible tunnel FET as footer transistor for power gating | Titash Rakshit, Rwik Sengupta | 2019-09-24 |
| 10381271 | Field effect transistor with stacked nanowire-like channels and methods of manufacturing the same | Borna J. Obradovic | 2019-08-13 |
| 10381315 | Method and system for providing a reverse-engineering resistant hardware embedded security module | Harsono S. Simka, Ganesh Hegde, Joon Goo Hong, Rwik Sengupta | 2019-08-13 |
| 10361195 | Semiconductor device with an isolation gate and method of forming | Rwik Sengupta | 2019-07-23 |
| 10312152 | Field effect transistor with stacked nanowire-like channels and methods of manufacturing the same | Borna J. Obradovic, Joon Goo Hong, Seung Hun Lee, Pan-Kwi Park, Seung-ryul Lee | 2019-06-04 |
| 10297673 | Methods of forming semiconductor devices including conductive contacts on source/drains | Jorge A. Kittl, Ganesh Hegde, Rwik Sengupta, Borna J. Obradovic | 2019-05-21 |
| 10283638 | Structure and method to achieve large strain in NS without addition of stack-generated defects | Jorge A. Kittl, Ganesh Hegde, Robert C. Bowen | 2019-05-07 |
| 10205025 | Methods to achieve strained channel finFET devices | Jorge A. Kittl, Joon Goo Hong, Dharmendar Reddy Palle | 2019-02-12 |
| 10199474 | Field effect transistor with decoupled channel and methods of manufacturing the same | Borna J. Obradovic | 2019-02-05 |
| 10181527 | FinFet having dual vertical spacer and method of manufacturing the same | Dharmendar Reddy Palle, Borna J. Obradovic, Joon Goo Hong | 2019-01-15 |
| 10170549 | Strained stacked nanosheet FETs and/or quantum well stacked nanosheet | Jorge A. Kittl, Borna J. Obradovic, Robert C. Bowen | 2019-01-01 |
| 10147793 | FinFET devices including recessed source/drain regions having optimized depths | Borna J. Obradovic, Jorge A. Kittl, Robert C. Bowen, Ryan M. Hatcher | 2018-12-04 |