Issued Patents All Time
Showing 126–150 of 167 patents
| Patent # | Title | Co-Inventors | Date |
|---|---|---|---|
| 6306712 | Sidewall process and method of implantation for improved CMOS with benefit of low CGD, improved doping profiles, and insensitivity to chemical processing | Mahalingam Nandakumar | 2001-10-23 |
| 6261887 | Transistors with independently formed gate structures and method | — | 2001-07-17 |
| 6258644 | Mixed voltage CMOS process for high reliability and high performance core and I/O transistors with reduced mask steps | Manoj Mehrotra, Mahalingam Nandakumar | 2001-07-10 |
| 6251761 | Process for polycrystalline silicon gates and high-K dielectric compatibility | Sunil Hattangady | 2001-06-26 |
| 6246091 | Lateral MOSFET having a barrier between the source/drain regions and the channel | — | 2001-06-12 |
| 6242295 | Method of fabricating a shallow doped region for a shallow junction transistor | Douglas T. Grider, Katherine E. Violette | 2001-06-05 |
| 6228725 | Semiconductor devices with pocket implant and counter doping | Mahalingam Nandakumar, Amitava Chatterjee, Ih-Chin Chen | 2001-05-08 |
| 6187641 | Lateral MOSFET having a barrier between the source/drain region and the channel region using a heterostructure raised source/drain region | William U. Liu | 2001-02-13 |
| 6160299 | Shallow-implant elevated source/drain doping from a sidewall dopant source | — | 2000-12-12 |
| 6127233 | Lateral MOSFET having a barrier between the source/drain regions and the channel region | — | 2000-10-03 |
| 6124627 | Lateral MOSFET having a barrier between the source/drain region and the channel region using a heterostructure raised source/drain region | William U. Liu | 2000-09-26 |
| 6093610 | Self-aligned pocket process for deep sub-0.1 .mu.m CMOS devices and the device | — | 2000-07-25 |
| 6087248 | Method of forming a transistor having thin doped semiconductor gate | — | 2000-07-11 |
| 6083836 | Transistors with substitutionally formed gate structures and method | — | 2000-07-04 |
| 6063675 | Method of forming a MOSFET using a disposable gate with a sidewall dielectric | — | 2000-05-16 |
| 6063677 | Method of forming a MOSFET using a disposable gate and raised source and drain | Richard A. Chapman | 2000-05-16 |
| 5976937 | Transistor having ultrashallow source and drain junctions with reduced gate overlap and method | Mahalingam Nandakumar | 1999-11-02 |
| 5917219 | Semiconductor devices with pocket implant and counter doping | Mahalingam Nandakumar, Amitava Chatterjee, Ih-Chin Chen | 1999-06-29 |
| 5918145 | Method of forming a microelectronic device incorporating low resistivity straps between regions | — | 1999-06-29 |
| 5793083 | Method for designing shallow junction, salicided NMOS transistors with decreased electrostatic discharge sensitivity | E. Ajith Amerasekera, Vincent M. McNeil | 1998-08-11 |
| 5629218 | Method for forming a field-effect transistor including a mask body and source/drain contacts | — | 1997-05-13 |
| 5548548 | Pass transistor for a 256 megabit dram with negatively biased substrate | Amitava Chatterjee, Jiann Liu, Purnendu K. Mozumder, Ih-Chin Chen | 1996-08-20 |
| 5504359 | Vertical FET device with low gate to source overlap capacitance | — | 1996-04-02 |
| 5475266 | Structure for microelectronic device incorporating low resistivity straps between conductive regions | — | 1995-12-12 |
| 5324961 | Stacked capacitor SRAM cell | — | 1994-06-28 |