Issued Patents All Time
Showing 25 most recent of 35 patents
| Patent # | Title | Co-Inventors | Date |
|---|---|---|---|
| 6828249 | System and method for enhanced monitoring of an etch process | Catherine Odor | 2004-12-07 |
| 6376293 | Shallow drain extenders for CMOS transistors using replacement gate design | — | 2002-04-23 |
| 6348719 | Using a change in doping of poly gate to permit placing both high voltage and low voltage transistors on the same chip | — | 2002-02-19 |
| 6207511 | Self-aligned trenched-channel lateral-current-flow transistor | Theodore W. Houston, Keith A. Joyner | 2001-03-27 |
| 6180978 | Disposable gate/replacement gate MOSFETs for sub-0.1 micron gate length and ultra-shallow junctions | Amitava Chatterjee, Syed Suhail Murtaza | 2001-01-30 |
| 6127232 | Disposable gate/replacement gate MOSFETS for sub-0.1 micron gate length and ultra-shallow junctions | Amitava Chatterjee, Syed Suhail Murtaza | 2000-10-03 |
| 6118161 | Self-aligned trenched-channel lateral-current-flow transistor | Theodore W. Houston, Keith A. Joyner | 2000-09-12 |
| 6063677 | Method of forming a MOSFET using a disposable gate and raised source and drain | Mark S. Rodder | 2000-05-16 |
| 6010929 | Method for forming high voltage and low voltage transistors on the same substrate | — | 2000-01-04 |
| 5976769 | Intermediate layer lithography | — | 1999-11-02 |
| 5933740 | RTP booster to semiconductor device anneal | — | 1999-08-03 |
| 5595922 | Process for thickening selective gate oxide regions | Howard L. Tigelaar, Bert R. Riemenschneider, Andrew T. Appel | 1997-01-21 |
| 5468666 | Using a change in doping of poly gate to permit placing both high voltage and low voltage transistors on the same chip | — | 1995-11-21 |
| 5389809 | Silicided MOS transistor | Roger A. Haken | 1995-02-14 |
| 5357459 | Nonvolatile capacitor random access memory | — | 1994-10-18 |
| 5227649 | Circuit layout and method for VLSI circuits having local interconnects | — | 1993-07-13 |
| 5198378 | Process of fabricating elevated source/drain transistor | Mark S. Rodder | 1993-03-30 |
| 5079180 | Method of fabricating a raised source/drain transistor | Mark S. Rodder | 1992-01-07 |
| 5010032 | Process for making CMOS device with both P+ and N+ gates including refractory metal silicide and nitride interconnects | Thomas E. Tang, Che-Chia Wei, Roger A. Haken | 1991-04-23 |
| 4998150 | Raised source/drain transistor | Mark S. Rodder | 1991-03-05 |
| 4962322 | Nonvolatible capacitor random access memory | — | 1990-10-09 |
| 4908327 | Counter-doped transistor | — | 1990-03-13 |
| 4892614 | Integrated circuit isolation process | Clarence W. Teng | 1990-01-09 |
| 4890141 | CMOS device with both p+ and n+ gates | Thomas E. Tang, Che-Chia Wei, Roger A. Haken | 1989-12-26 |
| 4845047 | Threshold adjustment method for an IGFET | Thomas C. Holloway, Roger A. Haken | 1989-07-04 |