Issued Patents All Time
Showing 25 most recent of 28 patents
| Patent # | Title | Co-Inventors | Date |
|---|---|---|---|
| 11570957 | Adjustable, controlled rate plant watering device | — | 2023-02-07 |
| 7459734 | Method for manufacturing and structure for transistors with reduced gate to contact spacing | Mark S. Rodder | 2008-12-02 |
| 7339214 | Methods and apparatus for inducing stress in a semiconductor device | Christoph Wasshuber | 2008-03-04 |
| 7101772 | Means for forming SOI | Theodore W. Houston | 2006-09-05 |
| 6806151 | Methods and apparatus for inducing stress in a semiconductor device | Christoph Wasshuber | 2004-10-19 |
| 6767777 | Method for manufacturing and structure for transistors with reduced gate to contact spacing including etching to thin the spacers | Mark S. Rodder | 2004-07-27 |
| 6737347 | Semiconductor device with fully self-aligned local interconnects, and method for fabricating the device | Theodore W. Houston | 2004-05-18 |
| 6376285 | Annealed porous silicon with epitaxial layer for SOI | Leland Swanson | 2002-04-23 |
| 6376859 | Variable porosity porous silicon isolation | Leland Swanson | 2002-04-23 |
| 6228747 | Organic sidewall spacers used with resist | — | 2001-05-08 |
| 6214699 | Method for forming an isolation structure in a substrate | — | 2001-04-10 |
| 6207511 | Self-aligned trenched-channel lateral-current-flow transistor | Richard A. Chapman, Theodore W. Houston | 2001-03-27 |
| 6180491 | Isolation structure and method | Lee M. Loewenstein | 2001-01-30 |
| 6171969 | Uniform dopant distribution for mesas of semiconductors | — | 2001-01-09 |
| 6118161 | Self-aligned trenched-channel lateral-current-flow transistor | Richard A. Chapman, Theodore W. Houston | 2000-09-12 |
| 6114741 | Trench isolation of a CMOS structure | Lee M. Loewenstein | 2000-09-05 |
| 6057214 | Silicon-on-insulation trench isolation structure and method for forming | — | 2000-05-02 |
| 6004871 | Implant enhancement of titanium silicidation | Jorge A. Kittl, George R. Misium | 1999-12-21 |
| 5982006 | Active silicon-on-insulator region having a buried insulation layer with tapered edge | — | 1999-11-09 |
| 5909628 | Reducing non-uniformity in a refill layer thickness for a semiconductor device | Amitava Chatterjee, Theodore W. Houston, Ih-Chin Chen, Agerico L. Esquirel, Somnath Nag +4 more | 1999-06-01 |
| 5882981 | Mesa isolation Refill Process for Silicon on Insulator Technology Using Flowage Oxides as the Refill Material | Rajan Rajgopal, Kelly Taylor, Thomas R. Seha | 1999-03-16 |
| 5863827 | Oxide deglaze before sidewall oxidation of mesa or trench | — | 1999-01-26 |
| 5548149 | Varying the thickness of the surface silicon layer in a silicon-on-insulator substrate | — | 1996-08-20 |
| 5440132 | Systems and methods for controlling the temperature and uniformity of a wafer during a SIMOX implantation process | James B. Hollingsworth | 1995-08-08 |
| 5429955 | Method for constructing semiconductor-on-insulator | Mohamed K. El-Ghor, Harold H. Hosack | 1995-07-04 |