Issued Patents All Time
Showing 76–100 of 106 patents
| Patent # | Title | Co-Inventors | Date |
|---|---|---|---|
| 9606803 | Highly integrated scalable, flexible DSP megamodule architecture | Timothy David Anderson, Joseph Zbiciak, Duc Quang Bui, Kai Chirca, Naveen Bhoria +3 more | 2017-03-28 |
| 9575901 | Programmable address-based write-through cache control | Raguram Damodaran, Naveen Bhoria, David Matthew Thompson | 2017-02-21 |
| 9557936 | Protection of memories, datapath and pipeline registers, and other storage elements by distributed delayed detection and correction of soft errors | Timothy David Anderson, Joseph Zbiciak, Kai Chirca, Naveen Bhoria, David Matthew Thompson +2 more | 2017-01-31 |
| RE46193 | Distributed power control for controlling power consumption based on detected activity of logic blocks | Timothy David Anderson, Lewis Nardini, Jose Luis Flores, Raguram Damodaran, Joseph Zbiciak +1 more | 2016-11-01 |
| 9390011 | Zero cycle clock invalidate operation | Naveen Bhoria, Raguram Damodaran | 2016-07-12 |
| 9298643 | Performance and power improvement on DMA writes to level two combined cache/SRAM that is cached in level one data cache and line is valid and dirty | Jonathan (Son) Hung Tran, Raguram Damodaran, Joseph Zbiciak | 2016-03-29 |
| 9268708 | Level one data cache line lock and enhanced snoop protocol during cache victims and writebacks to maintain level one data cache and level two cache coherence | Raguram Damodaran, Jonathan (Son) Hung Tran, David Matthew Thompson | 2016-02-23 |
| 9244837 | Zero cycle clock invalidate operation | Naveen Bhoria, Raguram Damodaran | 2016-01-26 |
| 9189331 | Programmable address-based write-through cache control | Raguram Damodaran, Naveen Bhoria | 2015-11-17 |
| 9075744 | Performance and power improvement on DMA writes to level two combined cache/SRAM that is caused in level one data cache and line is valid and dirty | Jonathan (Son) Hung Tran, Raguram Damodaran, Joseph Zbiciak | 2015-07-07 |
| 9075743 | Managing bandwidth allocation in a processing node using distributed arbitration | Raguram Damodaran, Dheera Balasubramanian, Roger Kyle Castille, David Quintin Bell | 2015-07-07 |
| 9009408 | Non-blocking, pipelined write allocates with allocate data merging in a multi-level cache system | Raguram Damodaran, David Matthew Thompson | 2015-04-14 |
| 9003122 | Level one data cache line lock and enhanced snoop protocol during cache victims and writebacks to maintain level one data cache and level two cache coherence | Raguram Damodaran, Jonathan (Son) Hung Tran, David Matthew Thompson | 2015-04-07 |
| 8970267 | Asynchronous clock dividers to reduce on-chip variations of clock timing | Raguram Damodaran, Ramakrishnan Venkatasubramanian | 2015-03-03 |
| 8904260 | Robust hamming code implementation for soft error detection, correction, and reporting in a multi-level cache system using dual banking memory scheme | Jonathan (Son) Hung Tran, Joseph Zbiciak, Krishna Chaithanya Gurram | 2014-12-02 |
| 8904110 | Distributed user controlled multilevel block and global cache coherence with accurate completion status | Raguram Damodaran | 2014-12-02 |
| 8904115 | Cache with multiple access pipelines | Raguram Damodaran, Jonathan (Son) Hung Tran, Timothy David Anderson, Sanjive Agarwala | 2014-12-02 |
| 8856446 | Hazard prevention for data conflicts between level one data cache line allocates and snoop writes | Jonathan (Son) Hung Tran, Raguram Damodaran, Krishna Chaithanya Gurram | 2014-10-07 |
| 8732398 | Enhanced pipelining and multi-buffer architecture for level two cache controller to minimize hazard stalls and optimize performance | Raguram Damodaran | 2014-05-20 |
| 8732416 | Requester based transaction status reporting in a system with multi-level memory | Raguram Damodaran, Ramakrishnan Venkatasubramanian, Dheera Balasubramanian, Naveen Bhoria | 2014-05-20 |
| 8707127 | Configurable source based/requestor based error detection and correction for soft errors in multi-level cache memory to minimize CPU interrupt service routines | Jonathan (Son) Hung Tran, Raguram Damodaran, Krishna Chaithanya Gurram | 2014-04-22 |
| 8694843 | Clock control of pipelined memory for improved delay fault testing | Ramakrishnan Venkatasubramanian, Sumant Dinkar Kale | 2014-04-08 |
| 8683137 | Cache pre-allocation of ways for pipelined allocate requests | David Matthew Thompson | 2014-03-25 |
| 8661199 | Efficient level two memory banking to improve performance for multiple source traffic and enable deeper pipelining of accesses by reducing bank stalls | Ramakrishnan Venkatasubramanian | 2014-02-25 |
| 8656105 | Optimizing tag forwarding in a two level cache system from level one to lever two controllers for cache coherence protocol for direct memory access transfers | Raguram Damodaran, Joseph Zbiciak, Jonathan (Son) Hung Tran | 2014-02-18 |