Issued Patents All Time
Showing 26–50 of 106 patents
| Patent # | Title | Co-Inventors | Date |
|---|---|---|---|
| 11816032 | Cache size change | Naveen Bhoria, David Matthew Thompson, Neelima Muralidharan | 2023-11-14 |
| 11803505 | Multicore bus architecture with wire reduction and physical congestion minimization via shared transaction channels | David Matthew Thompson, Timothy David Anderson, Joseph Zbiciak, Kai Chirca, Matthew D. Pierson | 2023-10-31 |
| 11789868 | Hardware coherence signaling protocol | David Matthew Thompson, Naveen Bhoria, Pete Michael Hippleheuser | 2023-10-17 |
| 11782718 | Implied fence on stream open | Naveen Bhoria, Kai Chirca, Timothy David Anderson, Duc Quang Bui, Son Hung Tran | 2023-10-10 |
| 11768733 | Error correcting codes for multi-master memory controller | David Matthew Thompson, Son Hung Tran | 2023-09-26 |
| 11762683 | Merging data for write allocate | David Matthew Thompson | 2023-09-19 |
| 11740930 | Global coherence operations | Naveen Bhoria, David Matthew Thompson, Neelima Muralidharan | 2023-08-29 |
| 11720495 | Multi-level cache security | David Matthew Thompson, Naveen Bhoria | 2023-08-08 |
| 11714754 | Shadow caches for level 2 cache controller | David Matthew Thompson, Naveen Bhoria | 2023-08-01 |
| 11687457 | Hardware coherence for memory controller | David Matthew Thompson, Naveen Bhoria | 2023-06-27 |
| 11675700 | Cache coherence shared state suppression | David Matthew Thompson, Timothy David Anderson, Kai Chirca | 2023-06-13 |
| 11675660 | Parallelized scrubbing transactions | David Matthew Thompson | 2023-06-13 |
| 11620236 | Prefetch kill and revival in an instruction cache | Bipin Prasad Heremagalur Ramaprasad, David Matthew Thompson, Hung Ong | 2023-04-04 |
| 11609818 | Pipelined read-modify-write operations in cache memory | David Matthew Thompson, Daniel Wu | 2023-03-21 |
| 11580024 | Memory pipeline control in a hierarchical memory system | Timothy David Anderson, Kai Chirca, David Matthew Thompson | 2023-02-14 |
| 11567874 | Prefetch management in a hierarchical cache system | Bipin Prasad Heremagalur Ramaprasad, David Matthew Thompson, Hung Ong | 2023-01-31 |
| 11537532 | Lookahead priority collection to support priority elevation | Raguram Damodaran, Ramakrishnan Venkatasubramanian, Joseph Zbiciak | 2022-12-27 |
| 11494224 | Controller with caching and non-caching modes | Timothy David Anderson, David Matthew Thompson | 2022-11-08 |
| 11487616 | Write control for read-modify-write operations in cache memory | Timothy David Anderson, David Matthew Thompson, Daniel Wu | 2022-11-01 |
| 11461127 | Pipeline arbitration | David Matthew Thompson | 2022-10-04 |
| 11416334 | Handling non-correctable errors | David Matthew Thompson | 2022-08-16 |
| 11392498 | Aliased mode for cache controller | Timothy David Anderson, Pramod Kumar Swami, Naveen Bhoria, David Matthew Thompson, Neelima Muralidharan | 2022-07-19 |
| 11321268 | Multicore bus architecture with wire reduction and physical congestion minimization via shared transaction channels | David Matthew Thompson, Timothy David Anderson, Joseph Zbiciak, Kai Chirca, Matthew D. Pierson | 2022-05-03 |
| 11321248 | Multiple-requestor memory access pipeline and arbiter | David Matthew Thompson | 2022-05-03 |
| 11314660 | Prefetch kill and revival in an instruction cache | Bipin Prasad Heremagalur Ramaprasad, David Matthew Thompson, Hung Ong | 2022-04-26 |