Issued Patents All Time
Showing 51–75 of 106 patents
| Patent # | Title | Co-Inventors | Date |
|---|---|---|---|
| 11314644 | Cache size change | Naveen Bhoria, David Matthew Thompson, Neelima Muralidharan | 2022-04-26 |
| 11307858 | Cache preload operations using streaming engine | Joseph Zbiciak, Timothy David Anderson, Jonathan (Son) Hung Tran, Kai Chirca, Daniel Wu +1 more | 2022-04-19 |
| 11307987 | Tag update bus for updated coherence state | David Matthew Thompson, Naveen Bhoria, Peter Michael Hippleheuser | 2022-04-19 |
| 11294707 | Global coherence operations | Naveen Bhoria, David Matthew Thompson, Neelima Muralidharan | 2022-04-05 |
| 11249842 | Error correcting codes for multi-master memory controller | David Matthew Thompson, Son Hung Tran | 2022-02-15 |
| 11243883 | Cache coherence shared state suppression | David Matthew Thompson, Timothy David Anderson, Kai Chirca | 2022-02-08 |
| 11237905 | Pipelined read-modify-write operations in cache memory | David Matthew Thompson, Daniel Wu | 2022-02-01 |
| 11194617 | Merging data for write allocate | David Matthew Thompson | 2021-12-07 |
| 11169924 | Prefetch management in a hierarchical cache system | Bipin Prasad Heremagalur Ramaprasad, David Matthew Thompson, Hung Ong | 2021-11-09 |
| 11144456 | Hardware coherence signaling protocol | David Matthew Thompson, Naveen Bhoria, Peter Michael Hippleheuser | 2021-10-12 |
| 11138117 | Memory pipeline control in a hierarchical memory system | Timothy David Anderson, Kai Chirca, David Matthew Thompson | 2021-10-05 |
| 11119776 | Cache management operations using streaming engine | Joseph Zbiciak, Timothy David Anderson, Jonathan (Son) Hung Tran, Kai Chirca, Daniel Wu +1 more | 2021-09-14 |
| 11106584 | Hardware coherence for memory controller | David Matthew Thompson, Naveen Bhoria | 2021-08-31 |
| 11106583 | Shadow caches for level 2 cache controller | David Matthew Thompson, Naveen Bhoria | 2021-08-31 |
| 11036648 | Highly integrated scalable, flexible DSP megamodule architecture | Timothy David Anderson, Joseph Zbiciak, Duc Quang Bui, Kai Chirca, Naveen Bhoria +3 more | 2021-06-15 |
| 10963255 | Implied fence on stream open | Naveen Bhoria, Kai Chirca, Timothy David Anderson, Duc Quang Bui, Son Hung Tran | 2021-03-30 |
| 10795844 | Multicore bus architecture with non-blocking high performance transaction credit system | David Matthew Thompson, Timothy David Anderson, Joseph Zbiciak, Kai Chirca, Matthew D. Pierson | 2020-10-06 |
| 10713180 | Lookahead priority collection to support priority elevation | Raguram Damodaran, Ramakrishnan Venkatasubramanian, Joseph Zbiciak | 2020-07-14 |
| 10642742 | Prefetch management in a hierarchical cache system | Bipin Prasad Heremagalur Ramaprasad, David Matthew Thompson, Hung Ong | 2020-05-05 |
| 10606596 | Cache preload operations using streaming engine | Joseph Zbiciak, Timothy David Anderson, Jonathan (Son) Hung Tran, Kai Chirca, Daniel Wu +1 more | 2020-03-31 |
| 10599433 | Cache management operations using streaming engine | Joseph Zbiciak, Timothy David Anderson, Jonathan (Son) Hung Tran, Kai Chirca, Daniel Wu +1 more | 2020-03-24 |
| 10489305 | Prefetch kill and revival in an instruction cache | Bipin Prasad Heremagalur Ramaprasad, David Matthew Thompson, Hung Ong | 2019-11-26 |
| 10311007 | Multicore bus architecture with non-blocking high performance transaction credit system | David Matthew Thompson, Timothy David Anderson, Joseph Zbiciak, Kai Chirca, Matthew D. Pierson | 2019-06-04 |
| 10162641 | Highly integrated scalable, flexible DSP megamodule architecture | Timothy David Anderson, Joseph Zbiciak, Duc Quang Bui, Kai Chirca, Naveen Bhoria +3 more | 2018-12-25 |
| 9904645 | Multicore bus architecture with non-blocking high performance transaction credit system | David Matthew Thompson, Timothy David Anderson, Joseph Zbiciak, Kai Chirca, Matthew D. Pierson | 2018-02-27 |