Issued Patents All Time
Showing 26–45 of 45 patents
| Patent # | Title | Co-Inventors | Date |
|---|---|---|---|
| 8352685 | Combining write buffer with dynamically adjustable flush metrics | Andrew J. Beaumont-Smith, Ramesh Gunna, Wei-Han Lien, Brian P. Lilly, Jaidev P. Patwardhan +2 more | 2013-01-08 |
| 8301843 | Data cache block zero implementation | Ramesh Gunna, Sudarshan Kadambi | 2012-10-30 |
| 8285937 | Fused store exclusive/memory barrier operation | Po-Yung Chang | 2012-10-09 |
| 8255671 | Processor employing split scheduler in which near, low latency operation dependencies are tracked separate from other operation dependencies | Andrew J. Beaumont-Smith, Honkai Tam, Daniel C. Murray, John H. Mylius, Pradeep Kanapathipillai | 2012-08-28 |
| 7707361 | Data cache block zero implementation | Ramesh Gunna, Sudarshan Kadambi | 2010-04-27 |
| 7152191 | Fault containment and error recovery in a scalable multiprocessor | Richard E. Kessler, Kourosh Gharachorloo, Thukalan V. Verghese | 2006-12-19 |
| 7024533 | Mechanism for synchronizing multiple skewed source-synchronous data channels with automatic initialization feature | Richard E. Kessler, Maurice B. Steinman, Scott E. Breach, Allen J. Baum, Gregg A. Bouchard | 2006-04-04 |
| 6678840 | Fault containment and error recovery in a scalable multiprocessor | Richard E. Kessler, Kourosh Gharachorloo, Thukalan V. Verghese | 2004-01-13 |
| 6662265 | Mechanism to track all open pages in a DRAM memory system | Richard E. Kessler, Maurice B. Steinman, Michael Bertone, Gregg A. Bouchard | 2003-12-09 |
| 6636955 | Mechanism for synchronizing multiple skewed source-synchronous data channels with automatic initialization feature | Richard E. Kessler, Maurice B. Steinman, Scott E. Breach, Allen J. Baum, Gregg A. Bouchard | 2003-10-21 |
| 6546453 | Proprammable DRAM address mapping mechanism | Richard E. Kessler, Maurice B. Steinman, Michael C. Braganza, Gregg A. Bouchard | 2003-04-08 |
| 6327667 | Apparatus and method for operating clock sensitive devices in multiple timing domains | Ricky C. Hetherington | 2001-12-04 |
| 6047357 | High speed method for maintaining cache coherency in a multi-level, set associative cache hierarchy | Elizabeth M. Cooper | 2000-04-04 |
| 5987544 | System interface protocol with optional module cache | Anil K. Jain, John H. Edmondson, Ruben Castelino | 1999-11-16 |
| 5805872 | Apparatus for generation of control signals from the read cycle rate and read speed of a memory | — | 1998-09-08 |
| 5630055 | Autonomous pipeline reconfiguration for continuous error correction for fills from tertiary cache or memory | Ruben Castelino, Chandrasekhara Somanathan | 1997-05-13 |
| 5615167 | Method for increasing system bandwidth through an on-chip address lock register | Anil K. Jain, John H. Edmondson | 1997-03-25 |
| 5214770 | System for flushing instruction-cache only when instruction-cache address and data-cache address are matched and the execution of a return-from-exception-or-interrupt command | Raj K. Ramanujan, Simon C. Steely, Jr. | 1993-05-25 |
| 5038278 | Cache with at least two fill rates | Simon C. Steely, Jr., Raj K. Ramanujan, Walter A. Beach | 1991-08-06 |
| 5003459 | Cache memory system | Raj K. Ramanujan, Simon C. Steely, Jr., David J. Sager | 1991-03-26 |