Issued Patents All Time
Showing 51–75 of 164 patents
| Patent # | Title | Co-Inventors | Date |
|---|---|---|---|
| 10763273 | Vertical GAA flash memory including two-transistor memory cells | Guan-Wei Wu, I-Chen Yang | 2020-09-01 |
| 10741262 | NAND flash operating techniques mitigating program disturbance | Wei-Liang Lin, Chun-Chang Lu, Wen-Jer Tsai, Guan-Wei Wu | 2020-08-11 |
| 10741250 | Non-volatile memory device and driving method thereof | Hsing-Wen Chang, Chi-Yuan Chin | 2020-08-11 |
| 10727399 | Top electrode cap structure for embedded memory | Tsung-Hsueh Yang | 2020-07-28 |
| 10727077 | Structure and method to expose memory cells with different sizes | Sheng-Chau Chen, Cheng-Tai Hsiao, Cheng-Yuan Tsai, Hsun-Chung Kuang | 2020-07-28 |
| 10713410 | Method for legalizing mixed-cell height standard cells of IC | Chao Wang, Yen-Yi Wu, Shih-Chun Chen, Meng-Kai Hsu | 2020-07-14 |
| 10658318 | Film scheme for bumping | Chern-Yow Hsu, Cheng-Yuan Tsai, Kong-Beng Thei | 2020-05-19 |
| 10558779 | Method of redistribution layer routing for 2.5-dimensional integrated circuit packages | Chun-Han Chiang, Fu-Yu Chuang, Chih-Che Lin, Chun-Yi Yang | 2020-02-11 |
| 10505103 | Top electrode cap structure for embedded memory | Tsung-Hsueh Yang | 2019-12-10 |
| 10497773 | Method to improve MIM device performance | Hsing-Lien Lin, Cheng-Yuan Tsai, Chia-Shiung Tsai | 2019-12-03 |
| 10468587 | Semiconductor structure, electrode structure and method of forming the same | Chung-Yen Chou, Fu-Ting Sung, Shih-Chang Liu | 2019-11-05 |
| 10290701 | MIM capacitor, semiconductor structure including MIM capacitors and method for manufacturing the same | — | 2019-05-14 |
| 10276779 | Top electrode cap structure for embedded memory | Tsung-Hsueh Yang | 2019-04-30 |
| 10275559 | Method for legalizing mixed-cell height standard cells of IC | Chao Wang, Yen-Yi Wu, Shih-Chun Chen, Meng-Kai Hsu | 2019-04-30 |
| 10176999 | Semiconductor device having a multi-layer, metal-containing film | Jian-Shiou Huang, Cheng-Yuan Tsai | 2019-01-08 |
| 10163651 | Structure and method to expose memory cells with different sizes | Sheng-Chau Chen, Cheng-Tai Hsiao, Cheng-Yuan Tsai, Hsun-Chung Kuang | 2018-12-25 |
| 10115896 | Semiconductor device and method of manufacturing the same | Hai-Dang Trinh, Cheng-Yuan Tsai, Chin-Wei Liang, Yen-Chang Chu | 2018-10-30 |
| 10103078 | Formation of getter layer for memory device | Cheng-Yuan Tsai, Kai-Wen Cheng | 2018-10-16 |
| 10047039 | Compounds, compositions and methods for treating tumors | Pei-Wen Hsieh, Ching-Ping Tseng, Yun-Zhan Tsai, Yu-Ling Huang | 2018-08-14 |
| 10043705 | Memory device and method of forming thereof | Yen-Chang Chu, Sheng-Chau Chen, Alexander Kalnitsky | 2018-08-07 |
| 9978457 | Method for operating memory array | Yung-Hsiang Chen, I-Chen Yang | 2018-05-22 |
| 9956191 | Composition of 5-nitrobenzoate derivatives as anti-metastatic agent that inhibits tumor cell-induced platelet aggregation | Ching-Ping Tseng, Pei-Wen Hsieh | 2018-05-01 |
| 9954166 | Embedded memory device with a composite top electrode | Hsing-Lien Lin, Hai-Dang Trinh | 2018-04-24 |
| 9940424 | Systems and methods for minimum-implant-area aware detailed placement | Kai-Han Tseng | 2018-04-10 |
| 9928334 | Redistribution layer routing for integrated fan-out wafer-level chip-scale packages | Bo-Qiao Lin, Ting-Chou Lin, Chun-Yi Yang | 2018-03-27 |