Issued Patents All Time
Showing 1–25 of 29 patents
| Patent # | Title | Co-Inventors | Date |
|---|---|---|---|
| 12424573 | Passivation scheme for pad openings and trenches | Ming-Hong Chang, Kun-Ming Huang, Po-Tao Chu, Shen-Ping Wang, Chien-Li Kuo | 2025-09-23 |
| 12163995 | GaN reliability built-in self test (BIST) apparatus and method for qualifying dynamic on-state resistance degradation | Yu-Ann LAI, Ruo-Rung HUANG, Kun-Lung Chen, Chan-Hong Chern | 2024-12-10 |
| 12002774 | Passivation scheme for pad openings and trenches | Ming-Hong Chang, Kun-Ming Huang, Po-Tao Chu, Shen-Ping Wang, Chien-Li Kuo | 2024-06-04 |
| 11680978 | GaN reliability built-in self test (BIST) apparatus and method for qualifying dynamic on-state resistance degradation | Yu-Ann LAI, Ruo-Rung HUANG, Kun-Lung Chen, Chan-Hong Chern | 2023-06-20 |
| 11444046 | Passivation scheme for pad openings and trenches | Ming-Hong Chang, Kun-Ming Huang, Po-Tao Chu, Shen-Ping Wang, Chien-Li Kuo | 2022-09-13 |
| 11341014 | System and method for generating a hotkey in a pre-boot environment | Craig L. Chaiken | 2022-05-24 |
| 11163886 | Information handling system firmware bit error detection and correction | Craig L. Chaiken | 2021-11-02 |
| 11011462 | Method for forming fuse pad and bond pad of integrated circuit | Tai-I Yang, Chih-Hao Lin, Hong-Seng Shue, Ruei-Hung Jang | 2021-05-18 |
| 10936460 | Method and apparatus for identifying and reporting faults at an information handling system | Craig L. Chaiken, Matthew Page, Michael W. Arms, Dustin A. Combs | 2021-03-02 |
| 10840371 | Ultra high voltage semiconductor device with electrostatic discharge capabilities | Tsai-Feng Yang, Chih-Heng Shen, Kun-Ming Huang, Po-Tao Chu, Shen-Ping Wang | 2020-11-17 |
| 10804231 | Passivation scheme for pad openings and trenches | Ming-Hong Chang, Kun-Ming Huang, Po-Tao Chu, Shen-Ping Wang, Chien-Li Kuo | 2020-10-13 |
| 10558779 | Method of redistribution layer routing for 2.5-dimensional integrated circuit packages | Chun-Han Chiang, Fu-Yu Chuang, Yao-Wen Chang, Chih-Che Lin | 2020-02-11 |
| 10461183 | Ultra high voltage semiconductor device with electrostatic discharge capabilities | Tsai-Feng Yang, Chih-Heng Shen, Kun-Ming Huang, Po-Tao Chu, Shen-Ping Wang | 2019-10-29 |
| 10312207 | Passivation scheme for pad openings and trenches | Ming-Hong Chang, Kun-Ming Huang, Po-Tao Chu, Shen-Ping Wang, Chien-Li Kuo | 2019-06-04 |
| 9928334 | Redistribution layer routing for integrated fan-out wafer-level chip-scale packages | Bo-Qiao Lin, Ting-Chou Lin, Yao-Wen Chang | 2018-03-27 |
| 9882046 | Ultra high voltage semiconductor device with electrostatic discharge capabilities | Tsai-Feng Yang, Chih-Heng Shen, Kun-Ming Huang, Po-Tao Chu, Shen-Ping Wang | 2018-01-30 |
| 9608060 | Isolation structure for semiconductor device | Yu-Chieh Chou, Tsai-Feng Yang, Kun-Ming Huang, Shen-Ping Wang, Lieh-Chuan Chen +1 more | 2017-03-28 |
| 9312348 | Ultra high voltage semiconductor device with electrostatic discharge capabilities | Tsai-Feng Yang, Kun-Ming Huang, Shen-Ping Wang, Chih-Heng Shen, Po-Tao Chu | 2016-04-12 |
| 7838947 | Read-only memory device coded with selectively insulated gate electrodes | — | 2010-11-23 |
| 7192811 | Read-only memory device coded with selectively insulated gate electrodes | — | 2007-03-20 |
| 6849526 | Method of improving device resistance | Jiun-Ren Lai, Shi-Xian Chen, Gwen Chang | 2005-02-01 |
| 6821684 | Method for fabricating mask ROM with self-aligned coding | Ta-Hung Yang | 2004-11-23 |
| 6794253 | Mask ROM structure and method of fabricating the same | Shang-Ping Lin, Tsung-Yi Chou, Hsiang-Pang Lee | 2004-09-21 |
| 6720629 | Structure of a memory device with buried bit line | Jiun-Ren Lai, Shi-Xian Chen, Gwen Chang | 2004-04-13 |
| 6649526 | Method for implanting and coding a read-only memory with automatic alignment at four corners | — | 2003-11-18 |