Issued Patents All Time
Showing 1–25 of 117 patents
| Patent # | Title | Co-Inventors | Date |
|---|---|---|---|
| 12431201 | Memory device and an operation method thereof | You-Liang CHOU | 2025-09-30 |
| 12308075 | Operation method for a memory device | Chih-Chieh Cheng, Chun-Chang Lu | 2025-05-20 |
| 12046293 | Memory device and method for operating selective erase scheme | Chun-Chang Lu, Wei-Liang Lin | 2024-07-23 |
| 11990202 | Data recovery method for memory device | You-Liang CHOU | 2024-05-21 |
| 11641744 | Method for fabricating memory device | Wei-Liang Lin | 2023-05-02 |
| 11600339 | Operation method for a memory device | Chih-Chieh Cheng, Chun-Chang Lu | 2023-03-07 |
| 11361824 | Memory device and operation method thereof | Shaw-Hung Ku, Cheng-Hsien Cheng, Chun-Chang Lu | 2022-06-14 |
| 11289502 | Memory device and method for fabricating the same | Wei-Liang Lin | 2022-03-29 |
| 11145674 | 3D memory device and method of manufacturing the same | Wei-Liang Lin | 2021-10-12 |
| 11062759 | Memory device and programming method thereof | Shaw-Hung Ku, Cheng-Hsien Cheng, Atsuhiro Suzuki, Yu-Hung Huang, Sheng-Kai Chen | 2021-07-13 |
| 11037632 | Multi-tier 3D memory and erase method thereof | Shaw-Hung Ku, Chih-Chieh Cheng, Cheng-Hsien Cheng, Yu-Hung Huang, Atsuhiro Suzuki | 2021-06-15 |
| 11018154 | Memory device and method for fabricating the same | Chun-Chang Lu, Guan-Wei Wu, Yao-Wen Chang | 2021-05-25 |
| 10950290 | Memory device and operating method thereof that reduce off current to reduce errors in reading and writing data which have plurality of memory cell blocks and a source voltage generator | Chun-Chang Lu | 2021-03-16 |
| 10741262 | NAND flash operating techniques mitigating program disturbance | Wei-Liang Lin, Chun-Chang Lu, Guan-Wei Wu, Yao-Wen Chang | 2020-08-11 |
| 10460797 | Method for programming non-volatile memory and memory system | Shaw-Hung Ku, Ta-Wei Lin, Cheng-Hsien Cheng, Chih-Wei Lee | 2019-10-29 |
| 10340017 | Erase-verify method for three-dimensional memories and memory system | Shaw-Hung Ku, Yu-Hung Huang, Cheng-Hsien Cheng, Chih-Wei Lee, Atsuhiro Suzuki | 2019-07-02 |
| 9830992 | Operation method of non-volatile memory cell and applications thereof | Wei-Liang Lin, Chih-Chieh Cheng | 2017-11-28 |
| 9786794 | Method of fabricating memory structure | Cheng-Hsien Cheng, Shih-Guei Yan, Chih-Chieh Cheng, Jyun-Siang Huang | 2017-10-10 |
| 9385240 | Memory device and method for fabricating the same | Chih-Chieh Cheng, Shih-Guei Yan, Nan Lu | 2016-07-05 |
| 9373629 | Memory device and method for fabricating the same | Shih-Guei Yan, Chih-Chieh Cheng | 2016-06-21 |
| 9349878 | Multi level programmable memory structure | Cheng-Hsien Cheng, Shih-Guei Yan, Chih-Chieh Cheng, Jyun-Siang Huang | 2016-05-24 |
| 9324431 | Floating gate memory device with interpoly charge trapping structure | Cheng-Hsien Cheng | 2016-04-26 |
| 9269583 | Method for fabricating memory device | Shih-Guei Yan, Chih-Chieh Cheng | 2016-02-23 |
| 9209198 | Memory cell and manufacturing method thereof | Chih-Chieh Cheng, Shih-Guei Yan | 2015-12-08 |
| 9209316 | ROM for constraining 2nd-bit effect | Chih-Chieh Cheng, Cheng-Hsien Cheng | 2015-12-08 |