Issued Patents All Time
Showing 1–22 of 22 patents
| Patent # | Title | Co-Inventors | Date |
|---|---|---|---|
| 11361824 | Memory device and operation method thereof | Cheng-Hsien Cheng, Chun-Chang Lu, Wen-Jer Tsai | 2022-06-14 |
| 11201169 | Memory device and method of fabricating the same | Chih-Hsiung Lee | 2021-12-14 |
| 11062759 | Memory device and programming method thereof | Cheng-Hsien Cheng, Atsuhiro Suzuki, Yu-Hung Huang, Sheng-Kai Chen, Wen-Jer Tsai | 2021-07-13 |
| 11037632 | Multi-tier 3D memory and erase method thereof | Chih-Chieh Cheng, Cheng-Hsien Cheng, Yu-Hung Huang, Atsuhiro Suzuki, Wen-Jer Tsai | 2021-06-15 |
| 10796753 | Method and system to determine quick pass write operation in increment step pulse programming operation | Yu-Hung Huang, Cheng-Hsien Cheng, Yin-Jen Chen | 2020-10-06 |
| 10644018 | 3D memory having plural lower select gates | Chih-Wei Lee, Cheng-Hsien Cheng, Atsuhiro Suzuki | 2020-05-05 |
| 10460797 | Method for programming non-volatile memory and memory system | Ta-Wei Lin, Cheng-Hsien Cheng, Chih-Wei Lee, Wen-Jer Tsai | 2019-10-29 |
| 10340017 | Erase-verify method for three-dimensional memories and memory system | Yu-Hung Huang, Cheng-Hsien Cheng, Chih-Wei Lee, Atsuhiro Suzuki, Wen-Jer Tsai | 2019-07-02 |
| 9859007 | Non-volatile memory device having multiple string select lines | Atsuhiro Suzuki, Chih-Wei Lee | 2018-01-02 |
| 9620603 | Semiconductor device with a P-N junction for reduced charge leakage and method of manufacturing the same | Chih-Hsiung Lee | 2017-04-11 |
| 9589982 | Structure and method of operation for improved gate capacity for 3D NOR flash memory | Cheng-Hsien Cheng, Chih-Wei Lee, Wen-Pin Lu | 2017-03-07 |
| 9548121 | Memory device having only the top poly cut | Chih-Wei Lee, Cheng-Hsien Cheng | 2017-01-17 |
| 9524784 | Device and method for improved threshold voltage distribution for non-volatile memory | Cheng-Hsien Cheng, Chih-Wei Lee, Wen-Pin Lu | 2016-12-20 |
| 9437612 | Three-dimensional memory | Chih-Wei Lee, Cheng-Hsien Cheng, Wen-Pin Lu | 2016-09-06 |
| 8859364 | Manufacturing method of non-volatile memory | Chi-Pei Lu, Chun-Lien Su | 2014-10-14 |
| 8664710 | Non-volatile memory and manufacturing method thereof | Chi-Pei Lu, Chun-Lien Su | 2014-03-04 |
| 8466508 | Non-volatile memory structure including stress material between stacked patterns | Shih-Chin Lee, Chia-Wei Wu, Shang-Wei Lin, Tzung-Ting Han, Ming-Shang Chen +1 more | 2013-06-18 |
| 7971177 | Design tool for charge trapping memory using simulated programming operations | Chia-Wei Wu, Ming-Shang Chen, Wenpin Lu | 2011-06-28 |
| 7889556 | Flash memory having insulating liners between source/drain lines and channels | Ten Hao Yeh, Shih-Chin Lee, Shang-Wei Lin, Chia-Wei Wu, Tzung-Ting Han +2 more | 2011-02-15 |
| 7668010 | Flash memory having insulating liners between source/drain lines and channels | Ten Hao Yeh, Shih-Chin Lee, Shang-Wei Lin, Chia-Wei Wu, Tzung-Ting Han +2 more | 2010-02-23 |
| 7439085 | Method and apparatus for electroluminescence | Chih Chieh Yeh, Tahui Wang, Chih-Yuan Lu | 2008-10-21 |
| 7301818 | Hole annealing methods of non-volatile memory cells | Wenpin Lu | 2007-11-27 |