Issued Patents All Time
Showing 51–75 of 154 patents
| Patent # | Title | Co-Inventors | Date |
|---|---|---|---|
| 11967560 | Integrated circuit | Chia-Tien Wu, Jiann-Tyng Tzeng | 2024-04-23 |
| 11948974 | Semiconductor device including vertical transistor with back side power structure | Te-Hsin Chiu, Jiann-Tyng Tzeng | 2024-04-02 |
| 11942469 | Backside conducting lines in integrated circuits | Wei-An Lai, Te-Hsin Chiu, Jiann-Tyng Tzeng, Chung-Hsing Wang | 2024-03-26 |
| 11942470 | Semiconductor device and method for manufacturing the same | Jiann-Tyng Tzeng | 2024-03-26 |
| 11935830 | Integrated circuit with frontside and backside conductive layers and exposed backside substrate | Te-Hsin Chiu, Wei-Cheng Lin, Jiann-Tyng Tzeng, Jiun-Wei Lu | 2024-03-19 |
| 11923301 | Method of manufacturing semiconductor device | Hui-Ting Yang, Wei-Cheng Lin, Jiann-Tyng Tzeng | 2024-03-05 |
| 11923300 | Two-dimensional (2D) metal structure | Jiann-Tyng Tzeng, Ken-Hsien Hsieh | 2024-03-05 |
| 11923297 | Apparatus and methods for generating a circuit with high density routing layout | Wei-An Lai, Wei-Cheng Lin, Jiann-Tyng Tzeng | 2024-03-05 |
| 11923273 | Method of manufacturing a semiconductor device | Chia-Tien Wu, Jiann-Tyng Tzeng | 2024-03-05 |
| 11916074 | Double rule integrated circuit layouts for a dual transmission gate | Hui-Zhong Zhuang, Jiann-Tyng Tzeng, Li-Chun Tien, Pin-Dai Sue, Wei-Cheng Lin | 2024-02-27 |
| 11908538 | Cell structures and power routing for integrated circuits | Jiann-Tyng Tzeng, Kam-Tou Sio | 2024-02-20 |
| 11908852 | Layout designs of integrated circuits having backside routing tracks | Wei-An Lai, Wei-Cheng Lin, Jiann-Tyng Tzeng | 2024-02-20 |
| 11901286 | Diagonal via pattern and method | Chih-Min HSIAO, Ching-Hsu Chang, Jiann-Tyng Tzeng | 2024-02-13 |
| 11894375 | Semiconductor structure and method of forming the same | Te-Hsin Chiu, Wei-Cheng Lin, Jiann-Tyng Tzeng | 2024-02-06 |
| 11862561 | Semiconductor devices with backside routing and method of forming same | Shang-Wen Chang, Yi-Hsun Chiu, Cheng-Chi Chuang, Ching-Wei Tsai, Wei-Cheng Lin +1 more | 2024-01-02 |
| 11862623 | Semiconductor device including source/drain contact having height below gate stack | Charles Chew-Yuen Young, Chih-Liang Chen, Chih-Ming Lai, Jiann-Tyng Tzeng, Shun Li Chen +3 more | 2024-01-02 |
| 11854786 | Deep lines and shallow lines in signal conducting paths | Wei-An Lai, Te-Hsin Chiu, Wei-Cheng Lin, Jiann-Tyng Tzeng, Chia-Tien Wu | 2023-12-26 |
| 11854974 | Advanced node interconnect routing methodology | Jiann-Tyng Tzeng | 2023-12-26 |
| 11842137 | Integrated circuit and method of manufacturing same | Chih-Liang Chen, Charles Chew-Yuen Young, Hui-Zhong Zhuang, Jiann-Tyng Tzeng, Shun Li Chen +1 more | 2023-12-12 |
| 11842967 | Semiconductor devices with backside power distribution network and frontside through silicon via | Kam-Tou Sio, Cheng-Chi Chuang, Chia-Tien Wu, Jiann-Tyng Tzeng, Wei-Cheng Lin | 2023-12-12 |
| 11842994 | Semiconductor device having staggered gate-stub-size profile and method of manufacturing same | Te-Hsin Chiu, Jiann-Tyng Tzeng | 2023-12-12 |
| 11817392 | Integrated circuit | Chia-Tien Wu, Jiann-Tyng Tzeng | 2023-11-14 |
| 11810949 | Semiconductor arrangement and method of making | Jiann-Tyng Tzeng | 2023-11-07 |
| 11797745 | Semiconductor device with reduced power and method of manufacturing the same | Ching-Yu Huang, Jiann-Tyng Tzeng | 2023-10-24 |
| 11784179 | Structure and method of power supply routing in semiconductor device | Jiann-Tyng Tzeng | 2023-10-10 |