Issued Patents All Time
Showing 26–50 of 154 patents
| Patent # | Title | Co-Inventors | Date |
|---|---|---|---|
| 12265775 | Semiconductor device with reduced power | Ching-Yu Huang, Jiann-Tyng Tzeng | 2025-04-01 |
| 12266657 | Hybrid cell-based device, layout, and method | Yu-Xuan Huang, Te-Hsin Chiu, Hou-Yu Chen, Kuan-Lun Cheng, Jiann-Tyng Tzeng | 2025-04-01 |
| 12261167 | Structure and method of power supply routing in semiconductor device | Jiann-Tyng Tzeng | 2025-03-25 |
| 12261116 | Backside signal routing | Ching-Yu Huang, Wei-Cheng Lin, Jiann-Tyng Tzeng, Yi-Kan Cheng | 2025-03-25 |
| 12255148 | Power distribution structure and method | Te-Hsin Chiu, Jiann-Tyng Tzeng | 2025-03-18 |
| 12255203 | Monolithic three dimensional integrated circuit | Kam-Tou Sio, Jiann-Tyng Tzeng | 2025-03-18 |
| 12255238 | Integrated circuit, system and method of forming same | Chih-Min HSIAO, Jiann-Tyng Tzeng | 2025-03-18 |
| 12237334 | Semiconductor structure | Wei-Cheng Lin, Jiann-Tyng Tzeng | 2025-02-25 |
| 12218057 | Integrated circuit with backside interconnections and method of making same | Te-Hsin Chiu, Wei-An Lai, Ching-Wei Tsai, Jiann-Tyng Tzeng | 2025-02-04 |
| 12204838 | Structure and method for tying off dummy gate in semiconductor device | Jiann-Tyng Tzeng, Meng-Hung Shen, Wei-An Lai | 2025-01-21 |
| 12183788 | Semiconductor arrangement comprising a source pad, gate pad, drain pad, backside interconnect line, and backside contact, and backside conductive line and method of making | Jiann-Tyng Tzeng | 2024-12-31 |
| 12148700 | Semiconductor device, and associated method and system | Wei-Cheng Lin, Jiann-Tyng Tzeng | 2024-11-19 |
| 12142611 | Semiconductor structure for reducing stray capacitance and method of forming the same | Wei-Cheng Lin, Jiann-Tyng Tzeng | 2024-11-12 |
| 12142563 | Dual power structure with efficient layout | Jiann-Tyng Tzeng | 2024-11-12 |
| 12131998 | Integrated circuit, system and method of forming same | Te-Hsin Chiu, Kam-Tou Sio, Wei-Cheng Lin, Jiann-Tyng Tzeng | 2024-10-29 |
| 12101922 | Memory device and layout, manufacturing method of the same | Te-Hsin Chiu, Jiann-Tyng Tzeng, Wei-An Lai | 2024-09-24 |
| 12094777 | Method for manufacturing semiconductor device | Wei-Cheng Lin, Jiann-Tyng Tzeng | 2024-09-17 |
| 12079559 | IC device layout method | Guo-Huei Wu, Wei-Cheng Lin, Hui-Zhong Zhuang, Jiann-Tyng Tzeng | 2024-09-03 |
| 12067341 | Semiconductor structure, device, and method | Jiann-Tyng Tzeng, Wei-Cheng Lin | 2024-08-20 |
| 12061856 | Semiconductor device including combination rows and method and system for generating layout diagram of same | Jiann-Tyng Tzeng | 2024-08-13 |
| 12039246 | Circuit layout | Kam-Tou Sio, Jiann-Tyng Tzeng | 2024-07-16 |
| 12021021 | Integrated circuit structure | Te-Hsin Chiu, Wei-Cheng Lin, Jiann-Tyng Tzeng | 2024-06-25 |
| 12009364 | Semiconductor device and manufacture thereof | Te-Hsin Chiu, Meng-Hung Shen, Jiann-Tyng Tzeng | 2024-06-11 |
| 11984441 | Integrated circuit with backside power rail and backside interconnect | Guo-Huei Wu, Jiann-Tyng Tzeng | 2024-05-14 |
| 11967596 | Power rail and signal conducting line arrangement | Guo-Huei Wu, Wei-Cheng Lin, Hui-Zhong Zhuang, Chih-Liang Chen, Li-Chun Tien +1 more | 2024-04-23 |