Issued Patents All Time
Showing 126–150 of 156 patents
| Patent # | Title | Co-Inventors | Date |
|---|---|---|---|
| 8415211 | Semiconductor device, method of fabricating the same, and patterning mask utilizied by the method | Yi-Chun Lin, Kuo-Ming Wu | 2013-04-09 |
| 8389341 | Lateral power MOSFET with high breakdown voltage and low on-resistance | Tsung-Yi Huang, Puo-Yu Chiang, Shun-Liang Hsu, Chyi-Chyuan Huang, Fu-Hsin Chen +1 more | 2013-03-05 |
| 8338906 | Schottky device | Ping-Chun Yeh, Der-Chyang Yeh, Mingo Liu | 2012-12-25 |
| 8129783 | Lateral power MOSFET with high breakdown voltage and low on-resistance | Tsung-Yi Huang, Puo-Yu Chiang, Shun-Liang Hsu | 2012-03-06 |
| 8114745 | High voltage CMOS devices | Chen-Bau Wu, Chien-Shao Tang, Robin Hsieh, Shun-Liang Hsu | 2012-02-14 |
| 8093663 | Semiconductor device, method of fabricating the same, and patterning mask utilized by the method | Yi-Chun Lin, Kuo-Ming Wu | 2012-01-10 |
| 7989890 | Lateral power MOSFET with high breakdown voltage and low on-resistance | Tsung-Yi Huang, Puo-Yu Chiang, Shun-Liang Hsu, Chyi-Chyuan Huang, Fu-Hsin Chen +1 more | 2011-08-02 |
| 7719064 | High voltage CMOS devices | Chen-Bau Wu, Chien-Shao Tang, Robin Hsieh, Shun-Liang Hsu | 2010-05-18 |
| 7602037 | High voltage semiconductor devices and methods for fabricating the same | Yi-Chun Lin, Chi-Chih Chen, Kuo-Ming Wu | 2009-10-13 |
| 7525150 | High voltage double diffused drain MOS transistor with medium operation voltage | Fu-Hsin Chen, Yi-Chun Lin | 2009-04-28 |
| 7525155 | High voltage transistor structure for semiconductor device | Fu-Hsin Chen | 2009-04-28 |
| 7521741 | Shielding structures for preventing leakages in high voltage MOS devices | Yu-Chang Jong, Yueh-Chiou Lin, Shun-Liang Hsu, Chi-Hsuen Chang, Te-Yin Hsia | 2009-04-21 |
| 7476591 | Lateral power MOSFET with high breakdown voltage and low on-resistance | Tsung-Yi Huang, Puo-Yu Chiang, Shun-Liang Hsu | 2009-01-13 |
| 7423319 | LDPMOS structure with enhanced breakdown voltage | Robin Hsieh, Tsai Chun Lin, Albert Zhongxing Yao, Pai-Kang Hsu, Tsung-Yi Huang | 2008-09-09 |
| 7372102 | Structure having a shallow trench-deep trench isolation region for a BiCMOS/CMOS technology | Kuan-Lun Chang, Tsyr-Shyang Liou, Chih-Min Chiang, Jun-Lin Tsai | 2008-05-13 |
| 7372104 | High voltage CMOS devices | Chen-Bau Wu, Chien-Shao Tang, Robin Hsieh, Shun-Liang Hsu | 2008-05-13 |
| 7250344 | Method of forming a shallow trench-deep trench isolation region for a BiCMOS/CMOS technology | Kuan-Lun Chang, Tsyr-Shyang Liou, Chih-Min Chiang, Jun-Lin Tsai | 2007-07-31 |
| 7221021 | Method of forming high voltage devices with retrograde well | Kuo-Ming Wu, Chen-Bau Wu, Shun-Liang Hsu | 2007-05-22 |
| 7196375 | High-voltage MOS transistor | Fu-Hsin Chen | 2007-03-27 |
| 7045414 | Method of fabricating high voltage transistor | Fu-Hsin Chen | 2006-05-16 |
| 7015086 | Method of forming a shallow trench-deep trench isolation region for a BiCMOS/CMOS technology | Kuan-Lun Chang, Tsyr-Shyang Liou, Chih-Min Chiang, Jun-Lin Tsai | 2006-03-21 |
| 6924531 | LDMOS device with isolation guard rings | Fu-Hsin Chen | 2005-08-02 |
| 6847061 | Elimination of implant damage during manufacture of HBT | Chun Lin Tsai, Denny Tang, Chih-Min Chiang, Kuan-Lun Chang, Tsyr Shyang | 2005-01-25 |
| 6590262 | High voltage ESD protection device with very low snapback voltage | Jyh-Min Jiang, Kuo-Chio Liu, Jian-Hsing Lee | 2003-07-08 |
| 6569730 | High voltage transistor using P+ buried layer | Jun-Lin Tsai, Jei-Feng Hwang, Kuo-Chio Liu | 2003-05-27 |