Issued Patents All Time
Showing 151–156 of 156 patents
| Patent # | Title | Co-Inventors | Date |
|---|---|---|---|
| 6396126 | High voltage transistor using P+ buried layer | Jun-Lin Tsai, Jyh-Min Jiang, Jei-Feng Hwang | 2002-05-28 |
| 6340833 | Integrated circuit polysilicon resistor having a silicide extension to achieve 100 % metal shielding from hydrogen intrusion | Jun-Lin Tsai, Yung-Lung Hsu | 2002-01-22 |
| 6323074 | High voltage ESD protection device with very low snapback voltage by adding as a p+ diffusion and n-well to the NMOS drain | Jyh-Min Jiang, Kuo-Chio Liu, Jian-Hsing Lee | 2001-11-27 |
| 6291304 | Method of fabricating a high voltage transistor using P+ buried layer | Jun-Lin Tsaz, Jyh-Min Jiang, Jei-Feng Hwang | 2001-09-18 |
| 6245609 | High voltage transistor using P+ buried layer | Jun-Lin Tsai, Jei-Feng Hwang, Kuo-Chio Liu | 2001-06-12 |
| 6165861 | Integrated circuit polysilicon resistor having a silicide extension to achieve 100% metal shielding from hydrogen intrusion | Jun-Lin Tsai, Yung-Lung Hsu | 2000-12-26 |