Issued Patents All Time
Showing 1–16 of 16 patents
| Patent # | Title | Co-Inventors | Date |
|---|---|---|---|
| D956488 | Core for food products mold | — | 2022-07-05 |
| 10671909 | Decreasing neural network inference times using softmax approximation | Yang Li, Sanjiv Kumar, Si Si, Cho-Jui Hsieh | 2020-06-02 |
| 9728533 | Aqueous cleaning techniques and compositions for use in semiconductor device manufacture | Chun-Li Chou, Shao-Yen Ku, Jui-Ping Chuang | 2017-08-08 |
| 8916429 | Aqueous cleaning techniques and compositions for use in semiconductor device manufacturing | Chun-Li Chou, Shao-Yen Ku, Jui-Ping Chuang | 2014-12-23 |
| 7259850 | Approach to improve ellipsometer modeling accuracy for solving material optical constants N & K | Chih-Ming Ke, Shinn-Sheng Yu | 2007-08-21 |
| 6642150 | Method for testing for blind hole formed in wafer layer | Chuan-Chieh Huang, Wen-Hsiang Tang, Ming-Shuo Yen, Chiang-Jen Peng | 2003-11-04 |
| 6350390 | Plasma etch method for forming patterned layer with enhanced critical dimension (CD) control | Chi Kang Liu, Chang-Jen Shieh | 2002-02-26 |
| 6267121 | Process to season and determine condition of a high density plasma etcher | Cheng-Hao Huang, Ming-Shuo Yen, Shih-Fang Chen, Wen-Hsiang Tang | 2001-07-31 |
| 6214739 | Method of metal etching with in-situ plasma cleaning | Cheng-Hao Huang, Wen-Hsiang Tang | 2001-04-10 |
| 6159660 | Opposite focus control to avoid keyholes inside a passivation layer | Hsin Chen, An-Min Chiang | 2000-12-12 |
| 6020241 | Post metal code engineering for a ROM | Jyh-Cheng You, Shau-Tsung Yu, Yi-Jing Chu | 2000-02-01 |
| 5962345 | Method to reduce contact resistance by means of in-situ ICP | Ming-Shuo Yen, Horng-Wen Chen | 1999-10-05 |
| 5811343 | Oxidation method for removing fluorine gas inside polysilicon during semiconductor manufacturing to prevent delamination of subsequent layer induced by fluorine outgassing dielectric | Yeh-Jye Wann, An-Min Chiang, Shaun Yu | 1998-09-22 |
| 5753548 | Method for preventing fluorine outgassing-induced interlevel dielectric delamination on P-channel FETS | Shau-Tsung Yu, An-Min Chiang, Yeh-Jye Wann | 1998-05-19 |
| 5707896 | Method for preventing delamination of interlevel dielectric layer over FET P.sup.+ doped polysilicon gate electrodes on semiconductor integrated circuits | An-Min Chiang, Shau-Tsung Yu, Yeh-Jye Wann | 1998-01-13 |
| 5658821 | Method of improving uniformity of metal-to-poly capacitors composed by polysilicon oxide and avoiding device damage | Hsin Chen, Sue-Mei Ku, Chih-Shih Wei | 1997-08-19 |