Issued Patents All Time
Showing 201–225 of 417 patents
| Patent # | Title | Co-Inventors | Date |
|---|---|---|---|
| 11735251 | Timing control circuit of memory device with tracking word line and tracking bit line | Xiu-Li YANG, Lu-Ping KONG, He-Zhou WAN | 2023-08-22 |
| 11735587 | Backside PN junction diode | Yu-Xuan Huang, Ching-Wei Tsai, Jam-Wem Lee, Kuo-Ji Chen | 2023-08-22 |
| 11735482 | Semiconductor device structure and methods of forming the same | Kuan-Ting Pan, Kuo-Cheng Chiang, Shang-Wen Chang, Ching-Wei Tsai, Chih-Hao Wang | 2023-08-22 |
| 11735594 | Integrated circuit structure and method with hybrid orientation for FinFET | Tzer-Min Shen, Zhiqiang Wu, Chung-Cheng Wu, Ching-Wei Tsai, Chih-Hao Wang +1 more | 2023-08-22 |
| 11728211 | Semiconductor device structure and methods of forming the same | Lin-Yu Huang, Li-Zhen Yu, Chia-Hao Chang, Cheng-Chi Chuang, Chih-Hao Wang | 2023-08-15 |
| 11728401 | Semiconductor structures and methods thereof | Chung-Wei Hsu, Kuo-Cheng Chiang, Mao-Lin Huang, Lung-Kun Chu, Jia-Ni Yu +1 more | 2023-08-15 |
| 11715764 | Semiconductor device structure and methods of forming the same | Lin-Yu Huang, Li-Zhen Yu, Cheng-Chi Chuang, Chih-Hao Wang | 2023-08-01 |
| 11715781 | Semiconductor devices with improved capacitors | Wang-Chun Huang, Ching-Wei Tsai, Chih-Hao Wang | 2023-08-01 |
| 11710667 | Gate-all-around device with trimmed channel and dipoled dielectric layer and methods of forming the same | Chung-Wei Hsu, Kuo-Cheng Chiang, Hou-Yu Chen, Ching-Wei Tsai, Chih-Hao Wang +3 more | 2023-07-25 |
| 11710737 | Hybrid semiconductor device | Jung-Chien Cheng, Kuo-Cheng Chiang, Shi Ning Ju, Guan-Lin Chen, Chih-Hao Wang | 2023-07-25 |
| 11705174 | Integrated circuit with asymmetric arrangements of memory arrays | Xiu-Li YANG, He-Zhou WAN, Ching-Wei Wu | 2023-07-18 |
| 11705175 | Shared decoder circuit and method | XiuLi YANG, Ching-Wei Wu, He-Zhou WAN, Luping KONG | 2023-07-18 |
| 11705488 | Nano-sheet-based devices with asymmetric source and drain configurations | Cheng-Ting Chung, Yu-Xuan Huang, Yi-Bo Liao, Ching-Wei Tsai | 2023-07-18 |
| 11699742 | Semiconductor device with varying numbers of channel layers and method of fabrication thereof | Cheng-Ting Chung | 2023-07-11 |
| 11699733 | Semiconductor devices | Cheng-Ting Chung, Ching-Wei Tsai | 2023-07-11 |
| 11688809 | Semiconductor device structure | Kuo-Cheng Ching, Kuan-Ting Pan, Chih-Hao Wang | 2023-06-27 |
| 11682707 | Contact formation method and related structure | Lin-Yu Huang, Li-Zhen Yu, Chia-Hao Chang, Cheng-Chi Chuang, Chih-Hao Wang | 2023-06-20 |
| 11676819 | Method for metal gate cut and structure thereof | Pei-Yu Wang, Zhi-Chang Lin, Ching-Wei Tsai | 2023-06-13 |
| 11670581 | Interconnect structure | Lin-Yu Huang, Li-Zhen Yu, Chia-Hao Chang, Cheng-Chi Chuang, Chih-Hao Wang | 2023-06-06 |
| 11670723 | Silicon channel tempering | Mao-Lin Huang, Lung-Kun Chu, Chung-Wei Hsu, Jia-Ni Yu, Kuo-Cheng Chiang +1 more | 2023-06-06 |
| 11670692 | Gate-all-around devices having self-aligned capping between channel and backside power rail | Chung-Wei Hsu, Lung-Kun Chu, Mao-Lin Huang, Jia-Ni Yu, Kuo-Cheng Chiang +1 more | 2023-06-06 |
| 11670550 | Nanostructure field-effect transistor device and method of forming | Guan-Lin Chen, Kuo-Cheng Chiang, Shi Ning Ju, Jung-Chien Cheng, Chih-Hao Wang | 2023-06-06 |
| 11664454 | Method for forming semiconductor device structure | Kuo-Cheng Chiang, Shi Ning Ju, Ching-Wei Tsai, Chih-Hao Wang | 2023-05-30 |
| 11664451 | Method and device for boosting performance of FinFETs via strained spacer | Kai-Chieh Yang, Li-Yang Chuang, Pei-Yu Wang, Wei Ju Lee, Ching-Wei Tsai | 2023-05-30 |
| 11664378 | Semiconductor device structure and methods of forming the same | Wen-Ting Lan, Shi Ning Ju, Kuo-Cheng Chiang, Chih-Hao Wang | 2023-05-30 |