Issued Patents All Time
Showing 251–275 of 417 patents
| Patent # | Title | Co-Inventors | Date |
|---|---|---|---|
| 11575027 | Dummy dielectric fin design for parasitic capacitance reduction | Kuo-Cheng Ching, Chih-Hao Wang, Shi Ning Ju | 2023-02-07 |
| 11575034 | Back end of line nanowire power switch transistors | Li-Yang Chuang, Ching-Wei Tsai, Wang-Chun Huang | 2023-02-07 |
| 11569234 | Semiconductor device structure and methods of forming the same | Kuan-Ting Pan, Kuo-Cheng Chiang, Shi Ning Ju, Yi-Ruei Jhan, Chih-Hao Wang | 2023-01-31 |
| 11563106 | Formation method of isolation feature of semiconductor device structure | Kuo-Cheng Ching, Shi Ning Ju, Kuan-Ting Pan, Chih-Hao Wang | 2023-01-24 |
| 11563109 | Semiconductor device structure and method for forming the same | Mao-Lin Huang, Lung-Kun Chu, Chung-Wei Hsu, Jia-Ni Yu, Chun-Fu Lu +2 more | 2023-01-24 |
| 11563001 | Air spacer and capping structures in semiconductor devices | Lin-Yu Huang, Chiao-Hao Chang, Cheng-Chi Chuang, Chih-Hao Wang, Ching-Wei Tsai | 2023-01-24 |
| 11557659 | Gate all around transistor device and fabrication methods thereof | Chih-Ching Wang, Chia-Ying Su, Wen-Hsing Hsieh, Chung-Wei Wu, Zhiqiang Wu | 2023-01-17 |
| 11538927 | Nanostructures and method for manufacturing the same | Kuo-Cheng Chiang, Yen-Ming Chen, Jung-Chien Cheng, Chih-Hao Wang | 2022-12-27 |
| 11532519 | Semiconductor device and method | Yi-Bo Liao, Kai-Chieh Yang, Ching-Wei Tsai | 2022-12-20 |
| 11532744 | Gate cut structure and method of forming the same | Chun-Yuan Chen, Pei-Yu Wang, Huan-Chieh Su, Yi-Hsun Chiu, Cheng-Chi Chuang +2 more | 2022-12-20 |
| 11532735 | Self-aligned epitaxy layer | Kuo-Cheng Chiang, Chih-Hao Wang | 2022-12-20 |
| 11532732 | Multi-gate device and method of fabrication thereof | Yi-Ruei Jhan, Kuan-Ting Pan, Kuo-Cheng Chiang, Chih-Hao Wang | 2022-12-20 |
| 11532725 | Method for forming sidewall spacers and semiconductor devices fabricated thereof | Kuan-Ting Pan, Kuo-Cheng Chiang, Shi Ning Ju, Yi-Ruei Jhan, Chih-Hao Wang | 2022-12-20 |
| 11532715 | Source/drain contacts for semiconductor devices and methods of forming | Ching-Wei Tsai, Yi-Bo Liao, Cheng-Ting Chung, Yu-Xuan Huang | 2022-12-20 |
| 11532711 | PMOSFET source drain | Cheng-Ting Chung | 2022-12-20 |
| 11532625 | Semiconductor device and method of fabrication thereof | Kuo-Cheng Ching, Shi Ning Ju, Ching-Wei Tsai, Chih-Hao Wang | 2022-12-20 |
| 11532622 | High performance MOSFETs having different device characteristics | Tetsu Ohtou, Ching-Wei Tsai, Jiun-Jia Huang, Chi-Hsing Hsu | 2022-12-20 |
| 11527534 | Gap-insulated semiconductor device | Jung-Chien Cheng, Shi Ning Ju, Guan-Lin Chen, Kuo-Cheng Chiang, Chih-Hao Wang | 2022-12-13 |
| 11521662 | Write circuit of memory device | Xiu-Li YANG, He-Zhou WAN, Wei-Yang Jiang | 2022-12-06 |
| 11522074 | Semiconductor device and manufacturing method thereof | Kuo-Cheng Ching, Chih-Hao Wang, Keng-Chu Lin, Shi Ning Ju | 2022-12-06 |
| 11508615 | Semiconductor device structure and methods of forming the same | Lin-Yu Huang, Li-Zhen Yu, Chia-Hao Chang, Cheng-Chi Chuang, Chih-Hao Wang | 2022-11-22 |
| 11502183 | Air gap in inner spacers and methods of fabricating the same in field-effect transistors | Chien Ning Yao, Bo-Feng Young, Sai-Hooi Yeong, Chih-Hao Wang | 2022-11-15 |
| 11502168 | Tuning threshold voltage in nanosheet transitor devices | Chung-Wei Hsu, Hou-Yu Chen, Chih-Hao Wang, Ching-Wei Tsai, Kuo-Cheng Chiang +3 more | 2022-11-15 |
| 11495677 | Semiconductor devices and methods of manufacturing thereof | Yi-Ruei Jhan, Kuan-Ting Pan, Kuo-Cheng Chiang, Chih-Hao Wang | 2022-11-08 |
| 11495598 | Hybrid scheme for improved performance for P-type and N-type FinFETs | Kuo-Cheng Chiang, Shi Ning Ju, Ching-Wei Tsai, Chih-Hao Wang | 2022-11-08 |