Issued Patents All Time
Showing 176–200 of 417 patents
| Patent # | Title | Co-Inventors | Date |
|---|---|---|---|
| 11848372 | Method and structure for reducing source/drain contact resistance at wafer backside | Huan-Chieh Su, Li-Zhen Yu, Chun-Yuan Chen, Cheng-Chi Chuang, Chih-Hao Wang | 2023-12-19 |
| 11837535 | Semiconductor devices including decoupling capacitors | Yu-Xuan Huang, Hou-Yu Chen, Ching-Wei Tsai, Chung-Hui Chen | 2023-12-05 |
| 11837538 | Conductive rail structure for semiconductor devices | Yi-Bo Liao, Wei Ju Lee, Cheng-Ting Chung, Hou-Yu Chen, Chun-Fu Cheng | 2023-12-05 |
| 11837504 | Self-aligned structure for semiconductor devices | Kuo-Cheng Chiang, Chih-Hao Wang, Shi Ning Ju, Kuan-Ting Pan | 2023-12-05 |
| 11830854 | Packaged semiconductor devices including backside power rails and methods of forming the same | Chi-Yi Chuang, Hou-Yu Chen | 2023-11-28 |
| 11830769 | Semiconductor device with air gaps and method of fabrication thereof | Chia-Hao Chang, Lin-Yu Huang, Li-Zhen Yu, Cheng-Chi Chuang, Chih-Hao Wang | 2023-11-28 |
| 11824058 | Method of forming semiconductor device | Kuo-Cheng Ching, Shi Ning Ju, Ching-Wei Tsai, Chih-Hao Wang | 2023-11-21 |
| 11824101 | High aspect ratio gate structure formation | Sai-Hooi Yeong, Chi On Chui, Kai-Hsuan Lee, Chih-Hao Wang | 2023-11-21 |
| 11817504 | Isolation structures and methods of forming the same in field-effect transistors | Shi Ning Ju, Kuo-Cheng Chiang, Guan-Lin Chen, Chih-Hao Wang | 2023-11-14 |
| 11811404 | Latch circuit, memory device and method | XiuLi YANG, He-Zhou WAN, Ching-Wei Wu, Wenchao Hao | 2023-11-07 |
| 11798944 | Integration of silicon channel nanostructures and silicon-germanium channel nanostructures | Shi Ning Ju, Kuo-Cheng Chiang, Chih-Hao Wang, Guan-Lin Chen | 2023-10-24 |
| 11798884 | Contact via formation | Lin-Yu Huang, Li-Zhen Yu, Chia-Hao Chang, Cheng-Chi Chuang, Chih-Hao Wang | 2023-10-24 |
| 11796779 | Light path adjustment mechanism | Wei-Szu Lin, Yu-Chen Chang, Chih-Chien Lin, Yu-Ting Cheng | 2023-10-24 |
| 11784235 | Negative capacitance transistor having a multilayer ferroelectric structure or a ferroelectric layer with a gradient doping profile | Chi-Hsing Hsu, Sai-Hooi Yeong, Chih-Yu Chang, Ching-Wei Tsai | 2023-10-10 |
| 11769539 | Integrated circuit with asymmetric arrangements of memory arrays | Xiu-Li YANG, He-Zhou WAN, Ching-Wei Wu | 2023-09-26 |
| 11764281 | Gate air spacer for fin-like field effect transistor | Chien Ning Yao, Bo-Feng Young, Sai-Hooi Yeong, Chih-Hao Wang | 2023-09-19 |
| 11764286 | Reducing parasitic capacitance for gate-all-around device by forming extra inner spacers | Kuo-Cheng Ching, Chih-Hao Wang, Shi Ning Ju | 2023-09-19 |
| 11756995 | Method of forming a semiconductor device structure having an isolation layer to isolate a conductive feature and a gate electrode layer | Lung-Kun Chu, Mao-Lin Huang, Chung-Wei Hsu, Jia-Ni Yu, Kuo-Cheng Chiang +1 more | 2023-09-12 |
| 11757021 | Semiconductor devices with fin-top hard mask and methods for fabrication thereof | Yi-Ruei Jhan, Kuan-Ting Pan, Kuo-Cheng Chiang, Chih-Hao Wang | 2023-09-12 |
| 11756959 | Structure and method of integrated circuit having decouple capacitance | Ching-Wei Tsai, Yu-Xuan Huang, Wei Ju Lee, Chun-Fu Cheng, Chung-Wei Wu | 2023-09-12 |
| 11742385 | Selective liner on backside via and method thereof | Lin-Yu Huang, Li-Zhen Yu, Chia-Hao Chang, Cheng-Chi Chuang, Chih-Hao Wang | 2023-08-29 |
| 11742415 | Fin-like field effect transistor patterning methods for achieving fin width uniformity | Kuo-Cheng Ching, Shi Ning Ju, Chih-Hao Wang | 2023-08-29 |
| 11735669 | Vertically-oriented complementary transistor | Chi-Yi Chuang, Hou-Yu Chen | 2023-08-22 |
| 11735647 | Method for forming semiconductor device | Wang-Chun Huang, Hou-Yu Chen, Chih-Hao Wang | 2023-08-22 |
| 11735641 | FinFET structure with airgap and method of forming the same | Chien Ning Yao, Kai-Hsuan Lee, Sai-Hooi Yeong, Wei-Yang Lee, Chih-Hao Wang | 2023-08-22 |