Issued Patents All Time
Showing 226–250 of 251 patents
| Patent # | Title | Co-Inventors | Date |
|---|---|---|---|
| 9691666 | Layout architecture for performance improvement | Lee-Chung Lu, Li-Chun Tien | 2017-06-27 |
| 9679915 | Integrated circuit with well and substrate contacts | Ming-Zhang Kuo, Ho-Chieh Hsieh, Kuo-Feng TSENG, Lee-Chung Lu, Cheng-Chung Lin +1 more | 2017-06-13 |
| 9659129 | Standard cell having cell height being non-integral multiple of nominal minimum pitch | Shang-Chih Hsieh, Ting-Wei Chiang, Chun-Fu Chen, Hsiang-Jen Tseng | 2017-05-23 |
| 9653393 | Method and layout of an integrated circuit | Wei-Yu Chen, Li-Chun Tien, Ting-Wei Chiang, Hsiang-Jen Tseng | 2017-05-16 |
| 9641161 | Flip-flop with delineated layout for reduced footprint | Chi-Lin Liu, Ting-Wei Chiang, Jerry Chang Jui Kao, Lee-Chung Lu, Shang-Chih Hsieh +1 more | 2017-05-02 |
| 9626472 | Method and system of forming layout design | Ting-Wei Chiang, Li-Chun Tien, Zhe-Wei Jiang | 2017-04-18 |
| 9536032 | Method and system of layout placement based on multilayer gridlines | Ting-Wei Chiang, Li-Chun Tien, Zhe-Wei Jiang | 2017-01-03 |
| 9501600 | Standard cells for predetermined function having different types of layout | Shang-Chih Hsieh, Ting-Wei Chiang, Chun-Fu Chen, Hsiang-Jen Tseng | 2016-11-22 |
| 9431381 | System and method of processing cutting layout and example switching circuit | Tung-Heng Hsieh, Chung-Te Lin, Sheng-Hsiung Wang, Ting-Wei Chiang, Li-Chun Tien | 2016-08-30 |
| 9425141 | Integrated circuit with elongated coupling | Tung-Heng Hsieh, Chung-Te Lin, Ting-Wei Chiang, Sheng-Hsiung Wang, Li-Chun Tien | 2016-08-23 |
| 9412700 | Semiconductor device and method of manufacturing semiconductor device | Tung-Heng Hsieh, Chung-Te Lin, Ting-Wei Chiang, Sheng-Hsiung Wang, Li-Chun Tien | 2016-08-09 |
| 9336348 | Method of forming layout design | Tung-Heng Hsieh, Chung-Te Lin, Sheng-Hsiung Wang, Min-Hsiung Chiang, Ting-Wei Chiang +1 more | 2016-05-10 |
| 9337290 | Layout architecture for performance improvement | Lee-Chung Lu, Li-Chun Tien | 2016-05-10 |
| 9317646 | Masks formed based on integrated circuit layout design having cell that includes extended active region | Lee-Chung Lu, Li-Chun Tien, Chang-Yu Wu | 2016-04-19 |
| 9245887 | Method and layout of an integrated circuit | Ting-Wei Chiang, Chun-Fu Chen, Hsiang-Jen Tseng, Wei-Yu Chen, Shang-Chih Hsieh +1 more | 2016-01-26 |
| 9213795 | Multiple via connections using connectivity rings | Chin-Hsiung Hsu, Huang-Yu Chen, Li-Chun Tien, Lee-Chung Lu, Cheng-I Huang +2 more | 2015-12-15 |
| 9202696 | Method for designing antenna cell that prevents plasma induced gate dielectric damage in semiconductor integrated circuits | Jen-Hang Yang, Chun-Fu Chen, Pin-Dai Sue | 2015-12-01 |
| 9158877 | Standard cell metal structure directly over polysilicon structure | Shang-Chih Hsieh, Ting-Wei Chiang, Chun-Fu Chen, Hsiang-Jen Tseng | 2015-10-13 |
| 9123565 | Masks formed based on integrated circuit layout design having standard cell that includes extended active region | Lee-Chung Lu, Li-Chun Tien, Chang-Yu Wu | 2015-09-01 |
| 9105466 | Integrated circuit | Lee-Chung Lu, Li-Chun Tien, Mei-Hui Huang | 2015-08-11 |
| 9098668 | Layout of an integrated circuit | Li-Chun Tien, Ting-Wei Chiang, Hsiang-Jen Tseng, Wei-Yu Chen | 2015-08-04 |
| 9087170 | Cell layout design and method | Chin-Hsiung Hsu, Yuan-Te Hou, Li-Chun Tien, Fang-Yu Fan, Wen-Hao Chen +1 more | 2015-07-21 |
| 8872269 | Antenna cell design to prevent plasma induced gate dielectric damage in semiconductor integrated circuits | Jen-Hang Yang, Chun-Fu Chen, Pin-Dai Sue | 2014-10-28 |
| 8813016 | Multiple via connections using connectivity rings | Chin-Hsiung Hsu, Huang-Yu Chen, Li-Chun Tien, Lee-Chung Lu, Cheng-I Huang +2 more | 2014-08-19 |
| 8607172 | Integrated circuits and methods of designing the same | Lee-Chung Lu, Li-Chun Tien, Mei-Hui Huang | 2013-12-10 |