Issued Patents All Time
Showing 201–225 of 251 patents
| Patent # | Title | Co-Inventors | Date |
|---|---|---|---|
| 10503863 | Integrated circuit and method of manufacturing same | Shih-Wei Peng, Chih-Liang Chen, Charles Chew-Yuen Young, Jiann-Tyng Tzeng, Shun Li Chen +1 more | 2019-12-10 |
| 10504837 | Semiconductor device including a conductive feature over an active region | Tung-Heng Hsieh, Chung-Te Lin, Ting-Wei Chiang, Sheng-Hsiung Wang, Li-Chun Tien | 2019-12-10 |
| 10446555 | Buried metal track and methods forming same | Pochun Wang, Ting-Wei Chiang, Chih-Ming Lai, Jung-Chan Yang, Ru-Gun Liu +6 more | 2019-10-15 |
| 10380315 | Integrated circuit and method of forming an integrated circuit | Ting-Wei Chiang, Lee-Chung Lu, Li-Chun Tien, Shun Li Chen | 2019-08-13 |
| 10380306 | Layout of standard cells for predetermined function in integrated circuits | Shang-Chih Hsieh, Ting-Wei Chiang, Chun-Fu Chen, Hsiang-Jen Tseng | 2019-08-13 |
| 10331838 | Semiconductor device with fill cells | Jung-Chan Yang, Ting-Wei Chiang, Yun-Xiang Lin, Tien-Yu Kuo, Shu-Yi Ying | 2019-06-25 |
| 10325900 | Integrated circuit and method of fabricating the same | Chung-Te Lin, Ting-Wei Chiang, Pin-Dai Sue, Li-Chun Tien | 2019-06-18 |
| 10296694 | Integrated circuit and method of manufacturing same | Ting-Wei Chiang, Li-Chun Tien | 2019-05-21 |
| 10289789 | System for designing integrated circuit layout and method of making the integrated circuit layout | Shang-Chih Hsieh, Ting-Wei Chiang, Chun-Fu Chen, Hsiang-Jen Tseng | 2019-05-14 |
| 10277227 | Semiconductor device layout | Pin-Dai Sue, Ting-Wei Chiang, Li-Chun Tien, Shun Li Chen | 2019-04-30 |
| 10269784 | Integrated circuit layout and method of configuring the same | Chung-Te Lin, Ting-Wei Chiang, Pin-Dai Sue, Li-Chun Tien | 2019-04-23 |
| 10270432 | Flip-flop with delineated layout for reduced footprint | Chi-Lin Liu, Ting-Wei Chiang, Jerry Chang Jui Kao, Lee-Chung Lu, Shang-Chih Hsieh +1 more | 2019-04-23 |
| 10163883 | Layout method for integrated circuit and layout of the integrated circuit | Cheok-Kei Lei, Yu Li, Chia-Wei Tseng, Zhe-Wei Jiang, Chi-Lin Liu +3 more | 2018-12-25 |
| 10163880 | Integrated circuit and method of fabricating the same | Chung-Te Lin, Ting-Wei Chiang, Pin-Dai Sue, Li-Chun Tien | 2018-12-25 |
| 10157902 | Semiconductor devices with cells comprising routing resources | Mao-Wei Chiu, Ting-Wei Chiang, Li-Chun Tien, Chi-Yu Lu | 2018-12-18 |
| 10157910 | Circuits and structures including tap cells and fabrication methods thereof | Jin Xu, Ting-Wei Chiang, Li-Chun Tien | 2018-12-18 |
| 10141256 | Semiconductor device and layout design thereof | Chung-Te Lin, Ting-Wei Chiang, Li-Chun Tien, Pin-Dai Sue | 2018-11-27 |
| 10127340 | Standard cell layout, semiconductor device having engineering change order (ECO) cells and method | Mao-Wei Chiu, Ting-Wei Chiang, Li-Chun Tien, Chi-Yu Lu | 2018-11-13 |
| 9991158 | Semiconductor device, layout of semiconductor device, and method of manufacturing semiconductor device | Tung-Heng Hsieh, Chung-Te Lin, Sheng-Hsiung Wang, Ting-Wei Chiang, Li-Chun Tien +1 more | 2018-06-05 |
| 9984191 | Cell layout and structure | Tung-Heng Hsieh, Sheng-Hsiung Wang, Yu-Cheng Yeh, Tsung-Chieh Tsai, Juing-Yi Wu +2 more | 2018-05-29 |
| 9899263 | Method of forming layout design | Tung-Heng Hsieh, Chung-Te Lin, Sheng-Hsiung Wang, Min-Hsiung Chiang, Ting-Wei Chiang +1 more | 2018-02-20 |
| 9846757 | Cell grid architecture for FinFET technology | Ting-Wei Chiang, Chung-Te Lin, Li-Chun Tien | 2017-12-19 |
| 9831230 | Standard cell layout, semiconductor device having engineering change order (ECO) cells and method | Li-Chun Tien, Ya-Chi Chou, Chun-Fu Chen, Ting-Wei Chiang, Hsiang-Jen Tseng | 2017-11-28 |
| 9806071 | Integrated circuit with elongated coupling | Tung-Heng Hsieh, Chung-Te Lin, Ting-Wei Chiang, Sheng-Hsiung Wang, Li-Chun Tien | 2017-10-31 |
| 9767243 | System and method of layout design for integrated circuits | Ting-Wei Chiang, Li-Chun Tien | 2017-09-19 |