Issued Patents All Time
Showing 401–425 of 458 patents
| Patent # | Title | Co-Inventors | Date |
|---|---|---|---|
| 8324046 | Poly resistor and poly eFuse design for replacement gate technology | Kong-Beng Thei | 2012-12-04 |
| 8304831 | Method and apparatus of forming a gate | Ming Zhu, Lee-Wee Teo, Han-Guan Chew | 2012-11-06 |
| 8304840 | Spacer structures of a semiconductor device | Lee-Wee Teo, Ming Zhu, Hui-Wen Lin, Bao-Ru Young | 2012-11-06 |
| 8304842 | Interconnection structure for N/P metal gates | Han-Guan Chew, Ming Zhu, Lee-Wee Teo | 2012-11-06 |
| 8304839 | Poly resistor and poly eFuse design for replacement gate technology | Kong-Beng Thei | 2012-11-06 |
| 8294216 | Integrating the formation of I/O and core MOS devices with MOS capacitors and resistors | Mong-Song Liang, Wen-Chih Yang, Chien-Liang Chen, Chii-Horng Li | 2012-10-23 |
| 8286114 | 3-dimensional device design layout | Kong-Beng Thei, Mong-Song Liang, Sheng-Chen Chung, Chih-Tsung Yao, Jung-Hui Kao +3 more | 2012-10-09 |
| 8258584 | Offset gate semiconductor device | Chun-Hung Chen, Lee-Wee Teo, Ming Zhu, Bao-Ru Young | 2012-09-04 |
| 8237201 | Layout methods of integrated circuits having unit MOS devices | Kong-Beng Thei, Jen-Bin Hsu, Chung Long Cheng, Mong-Song Liang | 2012-08-07 |
| 8237227 | Dummy gate structure for gate last process | Su-Chen Lai, Ming-Yuan Wu, Kong-Beng Thei, Chiung-Han Yeh, Hong-Dyi Chang +3 more | 2012-08-07 |
| 8216888 | Eliminating poly uni-direction line-end shortening using second cut | Kong-Beng Thei | 2012-07-10 |
| 8202776 | Method for protecting a gate structure during contact formation | Hong-Dyi Chang, Pei-Chao Su, Kong-Beng Thei, Hun-Jan Tao | 2012-06-19 |
| 8193586 | Sealing structure for high-K metal gate | Chien-Hao Chen, Hao-Ming Lien, Ssu-Yi Li, Jun-Lin Yeh, Kang-Cheng Lin +8 more | 2012-06-05 |
| 8183644 | Metal gate structure of a CMOS semiconductor device | Bao-Ru Young, Ming Zhu, Hui-Wen Lin, Lee-Wee Teo | 2012-05-22 |
| 8173491 | Standard cell architecture and methods with variable design rules | Oscar M. K. Law, Manoj Joshi, Kong-Beng Thei | 2012-05-08 |
| 8153498 | Downsize polysilicon height for polysilicon resistor integration of replacement gate process | Chen-Pin Hsu, Chung Long Cheng, Kong-Beng Thei | 2012-04-10 |
| 8143137 | Method of fabricating semiconductor device by thinning hardmask layers on frontside and backside of substrate | Han-Guan Chew, Ming Zhu, Lee-Wee Teo | 2012-03-27 |
| 8143131 | Method of fabricating spacers in a strained semiconductor device | Chen-Pin Hsu, Kong-Beng Thei | 2012-03-27 |
| 8125051 | Device layout for gate last process | Kong-Beng Thei, Chiung-Han Yeh, Mong-Song Liang, Hou-Ju Li, Ming-Yuan Wu +1 more | 2012-02-28 |
| 8120086 | Low leakage capacitors including portions in inter-layer dielectrics | Oscar M. K. Law, Kong-Beng Thei | 2012-02-21 |
| 8105891 | Method for tuning a work function of high-K metal gate devices | Chiung-Han Yeh, Sheng-Chen Chung, Kong-Beng Thei | 2012-01-31 |
| 8105929 | Gate control and endcap improvement | Kong-Beng Thei | 2012-01-31 |
| 8093116 | Method for N/P patterning in a gate last process | Sheng-Chen Chung, Kong-Beng Thei | 2012-01-10 |
| 8093120 | Integrating a first contact structure in a gate last process | Chiung-Han Yeh, Ming-Yuan Wu, Kong-Beng Thei, Mong-Song Liang | 2012-01-10 |
| 8058119 | Device scheme of HKMG gate-last process | Sheng-Chen Chung, Kong-Beng Thei | 2011-11-15 |