Issued Patents All Time
Showing 126–150 of 152 patents
| Patent # | Title | Co-Inventors | Date |
|---|---|---|---|
| 7773403 | Spacer patterns using assist layer for high density semiconductor devices | George Matamis, Tuan Pham, Masaaki Higashitani, Takashi Orimoto | 2010-08-10 |
| 7736973 | Non-volatile memory arrays having dual control gate cell structures and a thick control gate dielectric and methods of forming | Takashi Orimoto, George Matamis | 2010-06-15 |
| 7732275 | Methods of forming NAND flash memory with fixed charge | Takashi Orimoto, George Matamis, Henry Chien | 2010-06-08 |
| 7723186 | Method of forming memory with floating gates including self-aligned metal nanodots using a coupling layer | Vinod R. Purayath, George Matamis, Takashi Orimoto, Tuan Pham | 2010-05-25 |
| 7704832 | Integrated non-volatile memory and peripheral circuitry fabrication | Tuan Pham, Masaaki Higashitani, George Matamis, Takashi Orimoto | 2010-04-27 |
| 7619926 | NAND flash memory with fixed charge | Takashi Orimoto, George Matamis, Henry Chien | 2009-11-17 |
| 7615447 | Composite charge storage structure formation in non-volatile memory using etch stop technologies | Vinod R. Purayath, George Matamis, Takashi Orimoto | 2009-11-10 |
| 7592223 | Methods of fabricating non-volatile memory with integrated select and peripheral circuitry and post-isolation memory cell formation | Tuan Pham, Takashi Orimoto, Masaaki Higashitani, George Matamis | 2009-09-22 |
| 7592225 | Methods of forming spacer patterns using assist layer for high density semiconductor devices | George Matamis, Tuan Pham, Masaaki Higashitani, Takashi Orimoto | 2009-09-22 |
| 7582529 | Methods of fabricating non-volatile memory with integrated peripheral circuitry and pre-isolation memory cell formation | George Matamis, Takashi Orimoto, Masaaki Higashitani, Tuan Pham | 2009-09-01 |
| 7494870 | Methods of forming NAND memory with virtual channel | Henry Chien, George Matamis, Takashi Orimoto | 2009-02-24 |
| 7495282 | NAND memory with virtual channel | Takashi Orimoto, Henry Chien, George Matamis | 2009-02-24 |
| 7279410 | Method for forming inlaid structures for IC interconnections | Lynne A. Okada, Fei Wang | 2007-10-09 |
| 6767827 | Method for forming dual inlaid structures for IC interconnections | Lynne A. Okada, Fei Wang | 2004-07-27 |
| 6670265 | Low K dielectic etch in high density plasma etcher | Fei Wang, Angela T. Hui | 2003-12-30 |
| 6632707 | Method for forming an interconnect structure using a CVD organic BARC to mitigate via poisoning | Fei Wang, Lynne A. Okada, Ramkumar Subramanian, Calvin T. Gabriel, Lu You | 2003-10-14 |
| 6554046 | Substrate cleaving tool and method | Michael A. Bryan | 2003-04-29 |
| 6513564 | Nozzle for cleaving substrates | Michael A. Bryan | 2003-02-04 |
| 6514860 | Integration of organic fill for dual damascene process | Lynne A. Okada, Fei Wang | 2003-02-04 |
| 6424039 | Dual damascene process using sacrificial spin-on materials | Fei Wang, Bhanwar Singh | 2002-07-23 |
| 6297167 | In-situ etch of multiple layers during formation of local interconnects | Fei Wang, William G. En | 2001-10-02 |
| 6263941 | Nozzle for cleaving substrates | Michael A. Bryan | 2001-07-24 |
| 6221740 | Substrate cleaving tool and method | Michael A. Bryan | 2001-04-24 |
| 6057239 | Dual damascene process using sacrificial spin-on materials | Fei Wang, Bhanwar Singh | 2000-05-02 |
| 5920796 | In-situ etch of BARC layer during formation of local interconnects | Fei Wang, Allison Holbrook | 1999-07-06 |