Issued Patents All Time
Showing 76–100 of 739 patents
| Patent # | Title | Co-Inventors | Date |
|---|---|---|---|
| 11953934 | Memory system using asymmetric source-synchronous clocking | — | 2024-04-09 |
| 11955200 | Dram interface mode with improved channel integrity and efficiency at high signaling rates | — | 2024-04-09 |
| 11955165 | Memories and memory components with interconnected and redundant data interfaces | Ely Tsern, John Eric Linstadt, Thomas A. Giovannini, Scott C. Best, Kenneth L. Wright | 2024-04-09 |
| 11955198 | Area-efficient, width-adjustable signaling interface | — | 2024-04-09 |
| 11948619 | Protocol for memory power-mode control | Wayne F. Ellis, Wayne S. Richardson, Akash Bansal, Lawrence Lai, Kishore Ven Kasamsetty | 2024-04-02 |
| 11947474 | Multi-mode memory module and memory component | John Eric Linstadt, Kenneth L. Wright | 2024-04-02 |
| 11947468 | Memory access during memory calibration | Ian Shaeffer | 2024-04-02 |
| 11942182 | Memory and system supporting parallel and serial access modes | Scott C. Best, William N. Ng | 2024-03-26 |
| 11941256 | Maintenance operations in a DRAM | Robert E. Palmer, John W. Poulton | 2024-03-26 |
| 11941369 | Dual-domain combinational logic circuitry | John Eric Linstadt | 2024-03-26 |
| 11921576 | Memory device and repair method with column-based error code tracking | Brent Haukness | 2024-03-05 |
| 11914888 | Memory component with input/output data rate alignment | John Eric Linstadt, Torsten Partsch | 2024-02-27 |
| 11914508 | Memory controller supporting nonvolatile physical memory | Ely Tsern | 2024-02-27 |
| 11900981 | Protocol for refresh between a memory controller and a memory device | Brent Haukness | 2024-02-13 |
| 11899597 | High capacity memory system with improved command-address and chip-select signaling mode | Abhijit M. Abhyankar, Suresh Rajan | 2024-02-13 |
| 11899571 | Memory system with activate-leveling method | Craig E. Hampel | 2024-02-13 |
| 11893388 | Multiplier-accumulator processing pipelines and processing component, and methods of operating same | Cheng C. Wang, Valentin Ossman | 2024-02-06 |
| 11886272 | Dynamically changing data access bandwidth by selectively enabling and disabling data links | — | 2024-01-30 |
| 11862236 | Memory component for deployment in a dynamic stripe width memory system | John Eric Linstadt, Kenneth L. Wright | 2024-01-02 |
| 11862235 | Stacked semiconductor device | — | 2024-01-02 |
| 11853600 | Memory systems, modules, and methods for improved capacity | Scott C. Best | 2023-12-26 |
| 11842762 | System application of DRAM component with cache mode | Thomas Vogelsang, Michael Raymond Miller, Collins Williams | 2023-12-12 |
| 11836099 | Memory system with cached memory module operations | Kenneth L. Wright, John Eric Linstadt, Craig E. Hampel | 2023-12-05 |
| 11829241 | Serializing and deserializing stage testing | Angus William McLaren, Robert A. Heaton, Aaron Ali | 2023-11-28 |
| 11829307 | DRAM interface mode with interruptible internal transfer operation | Liji Gopalakrishnan, Brent Haukness | 2023-11-28 |