Issued Patents All Time
Showing 126–150 of 739 patents
| Patent # | Title | Co-Inventors | Date |
|---|---|---|---|
| 11710520 | Memory systems and methods for improved power management | James E. Harris | 2023-07-25 |
| 11709736 | Fault tolerant memory systems and components with interconnected and redundant data interfaces | Kenneth L. Wright | 2023-07-25 |
| 11705187 | Variable width memory module supporting enhanced error detection and correction | John Eric Linstadt, Kenneth L. Wright | 2023-07-18 |
| 11693625 | Logarithmic addition-accumulator circuitry, processing pipeline including same, and methods of operation | Cheng C. Wang | 2023-07-04 |
| 11689246 | Configurable, power supply voltage referenced single-ended signaling with ESD protection | John W. Poulton, Carl W. Werner | 2023-06-27 |
| 11683050 | Memory controller and method of data bus inversion using an error detection correction code | John Eric Linstadt | 2023-06-20 |
| 11681632 | Techniques for storing data and tags in different memory arrays | — | 2023-06-20 |
| 11675657 | Energy-efficient error-correction-detection storage | John Eric Linstadt, Liji Gopalakrishnan | 2023-06-13 |
| 11669379 | Controller that receives a cyclic redundancy check (CRC) code for both read and write data transmitted via bidirectional data link | Yuanlong Wang | 2023-06-06 |
| 11664907 | Periodic calibration for communication channels by drift tracking | Craig E. Hampel, Richard E. Perego | 2023-05-30 |
| 11664067 | Memory system component that enables clock-to-strobe skew compensation | — | 2023-05-30 |
| 11657006 | Low latency memory access | — | 2023-05-23 |
| 11653476 | Memory subsystem for a cryogenic digital system | John Eric Linstadt, Thomas Vogelsang | 2023-05-16 |
| 11651820 | Fast read speed memory device | Deepak C. Sekar, Gary B. Bronner | 2023-05-16 |
| 11650824 | Multiplier-accumulator circuitry having processing pipelines and methods of operating same | Cheng C. Wang | 2023-05-16 |
| 11646094 | Memory system with error detection | John Eric Linstadt | 2023-05-09 |
| 11646090 | DRAM retention test method for dynamic error correction | Ely Tsern, Suresh Rajan, Thomas Vogelsang | 2023-05-09 |
| 11645214 | Protocol including timing calibration between memory request and data transfer | Holden D. Jessup | 2023-05-09 |
| 11636915 | Command/address channel error detection | John Eric Linstadt | 2023-04-25 |
| 11630607 | High capacity, high performance memory system | — | 2023-04-18 |
| 11625346 | Interface for memory readout from a memory component in the event of fault | Kenneth L. Wright | 2023-04-11 |
| 11621030 | Protocol for memory power-mode control | Wayne F. Ellis, Wayne S. Richardson, Akash Bansal, Lawrence Lai, Kishore Ven Kasamsetty | 2023-04-04 |
| 11609870 | Off-module data buffer | Christopher Haywood | 2023-03-21 |
| 11604645 | MAC processing pipelines having programmable granularity, and methods of operating same | Cheng C. Wang | 2023-03-14 |
| 11600349 | Testing through-silicon-vias | Thomas Vogelsang, William N. Ng | 2023-03-07 |