Issued Patents All Time
Showing 176–200 of 739 patents
| Patent # | Title | Co-Inventors | Date |
|---|---|---|---|
| 11451218 | Data transmission using delayed timing signals | Ely Tsern, Brian S. Leibowitz, Jared L. Zerbe | 2022-09-20 |
| 11442881 | MAC processing pipelines, circuitry to control and configure same, and methods of operating same | Cheng C. Wang | 2022-09-13 |
| 11405174 | Signaling system with adaptive timing calibration | Bret G. Stott, Craig E. Hampel | 2022-08-02 |
| 11403030 | Memory component with input/output data rate alignment | John Eric Linstadt, Torsten Partsch | 2022-08-02 |
| 11393550 | Memory system with error detection | John Eric Linstadt | 2022-07-19 |
| 11392452 | Serializing and deserializing stage testing | Angus William McLaren, Robert A. Heaton, Aaron Ali | 2022-07-19 |
| 11385959 | Memory repair method and apparatus based on error code tracking | Ely Tsern | 2022-07-12 |
| 11379392 | Multi-mode memory module and memory component | John Eric Linstadt, Kenneth L. Wright | 2022-07-05 |
| 11379136 | Adjustable access energy and access latency memory system and devices | John Eric Linstadt | 2022-07-05 |
| 11361839 | Command/address channel error detection | John Eric Linstadt | 2022-06-14 |
| 11349496 | Memory controller and method of data bus inversion using an error detection correction code | John Eric Linstadt | 2022-05-31 |
| 11347665 | Memory module threading with staggered data transfers | Hongzhong Zheng | 2022-05-31 |
| 11347608 | Memory module with dedicated repair devices | Brent Haukness, John Eric Linstadt, Scott C. Best | 2022-05-31 |
| 11347441 | Memory component having internal read-modify-write operation | Thomas Vogelsang | 2022-05-31 |
| 11340686 | Optimizing power in a memory device | Dinesh Patil, Amir Amirkhany, Farrukh Aquil, Kambiz Kaviani | 2022-05-24 |
| 11341070 | Dynamic random access memory (DRAM) component for high-performance, high-capacity registered memory modules | Ely Tsern, John Eric Linstadt, Thomas J. Giovannini, Kenneth L. Wright | 2022-05-24 |
| 11340973 | Controller that receives a cyclic redundancy check (CRC) code for both read and write data transmitted via bidirectional data link | Yuanlong Wang | 2022-05-24 |
| 11327831 | Energy-efficient error-correction-detection storage | John Eric Linstadt, Liji Gopalakrishnan | 2022-05-10 |
| 11323118 | Low power logic circuitry | John Eric Linstadt | 2022-05-03 |
| 11317510 | Load reduced memory module | Suresh Rajan | 2022-04-26 |
| 11314681 | Memory system with independently adjustable core and interface data rates | — | 2022-04-26 |
| 11314669 | Deterministic operation of storage class memory | Brent Haukness | 2022-04-26 |
| 11314504 | Multiplier-accumulator processing pipelines and processing component, and methods of operating same | Cheng C. Wang, Valentin Ossman | 2022-04-26 |
| 11309017 | Memory systems and methods for improved power management | James E. Harris | 2022-04-19 |
| 11309015 | Floating body DRAM with reduced access energy | John Eric Linstadt, Zhichao Lu, Kenneth L. Wright | 2022-04-19 |