Issued Patents All Time
Showing 1–25 of 207 patents
| Patent # | Title | Co-Inventors | Date |
|---|---|---|---|
| 12411779 | High bandwidth memory system | Krishna T. Malladi, Dimin Niu | 2025-09-09 |
| 12346286 | Two-dimensional processing array with a vertically stacked memory tile array | Shuangchen Li, Zhe Zhang, Dimin Niu | 2025-07-01 |
| 12346797 | Programmable access engine architecture for graph neural network and graph application | Heng Liu, Shuangchen Li, Tianchan GUAN | 2025-07-01 |
| 12340101 | Scaling out architecture for dram-based processing unit (DPU) | Dimin Niu, Shuangchen Li, Bob Brennan, Krishna T. Malladi | 2025-06-24 |
| 12332828 | Graph acceleration solution with cloud FPGA | Shuangchen Li, Dimin Niu, Zhe Zhang, Yuhao Wang | 2025-06-17 |
| 12321639 | Hybrid solid state drive (SSD) architecture using MRAM and NAND for improved power loss protection and performance | Fei Xue, Wentao Wu, Jiajing Jin, Xiang Gao, Jifeng Wang +2 more | 2025-06-03 |
| 12282654 | Effective transaction table with page bitmap | Dongyan Jiang | 2025-04-22 |
| 12271802 | Computing system for implementing artificial neural network models and method for implementing artificial neural network models | Tianchan GUAN, Shengcheng Wang, Dimin Niu | 2025-04-08 |
| 12248402 | Bandwidth boosted stacked memory | Krishna T. Malladi, Mu-Tien Chang, Dimin Niu | 2025-03-11 |
| 12248400 | Systems and methods for memory bandwidth allocation | Lide Duan, Bowen Huang, Qichen ZHANG, Shengcheng Wang, Yen-Kuang Chen | 2025-03-11 |
| 12242344 | DRAM assist error correction mechanism for DDR SDRAM interface | Dimin Niu, Mu-Tien Chang, Hyun-Joong Kim, Won-Hyung Song, Jangseok Choi | 2025-03-04 |
| 12222871 | Methods and apparatuses for addressing memory caches | Trung Diep | 2025-02-11 |
| 12216537 | Error detection, prediction and handling techniques for system-in-package memory architectures | Dimin Niu, Tianchan GUAN, Shuangchen Li | 2025-02-04 |
| 12216923 | Computer system, memory expansion device and method for use in computer system | Yijin GUAN, Tianchan GUAN, Dimin Niu | 2025-02-04 |
| 12210768 | Flexible memory extension systems and methods | Dimin Niu, Yijin GUAN, Shengcheng Wang, Yuhao Wang, Shuangchen Li | 2025-01-28 |
| 12204469 | Unsuccessful write retry buffer | Brent Haukness | 2025-01-21 |
| 12197726 | 3D-stacked memory with reconfigurable compute logic | Mu-Tien Chang, Prasun Gera, Dimin Niu | 2025-01-14 |
| 12197354 | Memory module threading with staggered data transfers | Frederick A. Ware | 2025-01-14 |
| 12189539 | Data processing system and memory management method of data processing system | Dimin Niu, Yijin GUAN, Tianchan GUAN, Shuangchen Li | 2025-01-07 |
| 12189546 | Asynchronous communication protocol compatible with synchronous DDR protocol | Dimin Niu, Mu-Tien Chang, Sun-Young Lim, Indong Kim, Jangseok Choi +1 more | 2025-01-07 |
| 12181987 | HBM RAS cache architecture | Dimin Niu, Krishna T. Malladi | 2024-12-31 |
| 12164593 | Dataflow accelerator architecture for general matrix-matrix multiplication and tensor computation in deep learning | Peng Gu, Krishna T. Malladi, Dimin Niu | 2024-12-10 |
| 12153646 | Adaptive matrix multiplication accelerator for machine learning and deep learning applications | Dongyan Jiang, Dimin Niu | 2024-11-26 |
| 12147341 | Memory controller prioritizing writing compressed data | Dimin Niu, Tianchan GUAN, Lide Duan | 2024-11-19 |
| 12141438 | Zero skipping techniques for reducing data movement | Fei Xue, Fei Sun, Yangjie ZHOU, Lide Duan | 2024-11-12 |