Issued Patents All Time
Showing 1–25 of 56 patents
| Patent # | Title | Co-Inventors | Date |
|---|---|---|---|
| 12248402 | Bandwidth boosted stacked memory | Krishna T. Malladi, Dimin Niu, Hongzhong Zheng | 2025-03-11 |
| 12242344 | DRAM assist error correction mechanism for DDR SDRAM interface | Dimin Niu, Hongzhong Zheng, Hyun-Joong Kim, Won-Hyung Song, Jangseok Choi | 2025-03-04 |
| 12197726 | 3D-stacked memory with reconfigurable compute logic | Prasun Gera, Dimin Niu, Hongzhong Zheng | 2025-01-14 |
| 12189546 | Asynchronous communication protocol compatible with synchronous DDR protocol | Dimin Niu, Hongzhong Zheng, Sun-Young Lim, Indong Kim, Jangseok Choi +1 more | 2025-01-07 |
| 12032828 | Coordinated in-module RAS features for synchronous DDR compatible memory | Dimin Niu, Hongzhong Zheng, Sun-Young Lim, Indong Kim, Jangseok Choi | 2024-07-09 |
| 11940922 | ISA extension for high-bandwidth memory | Krishna T. Malladi, Dimin Niu, Hongzhong Zheng | 2024-03-26 |
| 11789610 | 3D-stacked memory with reconfigurable compute logic | Prasun Gera, Dimin Niu, Hongzhong Zheng | 2023-10-17 |
| 11625296 | DRAM assist error correction mechanism for DDR SDRAM interface | Dimin Niu, Hongzhong Zheng, Hyun-Joong Kim, Won-Hyung Song, Jangseok Choi | 2023-04-11 |
| 11568920 | Dual row-column major dram | Dimin Niu, Hongzhong Zheng | 2023-01-31 |
| 11556476 | ISA extension for high-bandwidth memory | Krishna T. Malladi, Dimin Niu, Hongzhong Zheng | 2023-01-17 |
| 11513965 | Bandwidth boosted stacked memory | Krishna T. Malladi, Dimin Niu, Hongzhong Zheng | 2022-11-29 |
| 11397698 | Asynchronous communication protocol compatible with synchronous DDR protocol | Dimin Niu, Hongzhong Zheng, Sun-Young Lim, Indong Kim, Jangseok Choi +1 more | 2022-07-26 |
| 11294571 | Coordinated in-module RAS features for synchronous DDR compatible memory | Dimin Niu, Hongzhong Zheng, Sun-Young Lim, Indong Kim, Jangseok Choi | 2022-04-05 |
| 11175853 | Systems and methods for write and flush support in hybrid memory | Dimin Niu, Hongzhong Zheng, Heehyun Nam, Youngjin Cho, Sun-Young Lim | 2021-11-16 |
| 11079936 | 3-D stacked memory with reconfigurable compute logic | Prasun Gera, Dimin Niu, Hongzhong Zheng | 2021-08-03 |
| 11029879 | Page size synchronization and page size aware scheduling method for non-volatile memory dual in-line memory module (NVDIMM) over memory channel | Dimin Niu, Hongzhong Zheng, Sun-Young Lim, Jae Gon Lee, Indong Kim | 2021-06-08 |
| 11010242 | DRAM assist error correction mechanism for DDR SDRAM interface | Dimin Niu, Hongzhong Zheng, Hyun-Joong Kim, Won-Hyung Song, Jangseok Choi | 2021-05-18 |
| 10977118 | DRAM assist error correction mechanism for DDR SDRAM interface | Dimin Niu, Hongzhong Zheng, Hyun-Joong Kim, Won-Hyung Song, Jangseok Choi | 2021-04-13 |
| 10929026 | Multi-cell structure for non-volatile resistive memory | Dimin Niu, Hongzhong Zheng | 2021-02-23 |
| 10915451 | Bandwidth boosted stacked memory | Krishna T. Malladi, Dimin Niu, Hongzhong Zheng | 2021-02-09 |
| 10908993 | Method to deliver in-DRAM ECC information through DDR bus | Dimin Niu, Hongzhong Zheng, Hyun-Joong Kim, Won-Hyung Song, Jangseok Choi | 2021-02-02 |
| 10866897 | Byte-addressable flash-based memory module with prefetch mode that is adjusted based on feedback from prefetch accuracy that is calculated by comparing first decoded address and second decoded address, where the first decoded address is sent to memory controller, and the second decoded address is sent to prefetch buffer | Dimin Niu, Dongyan Jiang, Hongzhong Zheng | 2020-12-15 |
| 10866900 | ISA extension for high-bandwidth memory | Krishna T. Malladi, Dimin Niu, Hongzhong Zheng | 2020-12-15 |
| 10824348 | Method of executing conditional data scrubbing inside a smart storage device | Sompong Paul Olarig | 2020-11-03 |
| 10810144 | System and method for operating a DRR-compatible asynchronous memory module | Sun-Young Lim, Dimin Niu, Hongzhong Zheng, Indong Kim | 2020-10-20 |