Issued Patents All Time
Showing 51–75 of 207 patents
| Patent # | Title | Co-Inventors | Date |
|---|---|---|---|
| 11789610 | 3D-stacked memory with reconfigurable compute logic | Mu-Tien Chang, Prasun Gera, Dimin Niu | 2023-10-17 |
| 11775294 | Memory lookup computing mechanisms | Peng Gu, Krishna T. Malladi | 2023-10-03 |
| 11762776 | Cache access method and associated graph neural network system | Zhe Zhang, Shuangchen Li | 2023-09-19 |
| 11755507 | Memory module threading with staggered data transfers | Frederick A. Ware | 2023-09-12 |
| 11729268 | Computer-implemented method, system, and storage medium for prefetching in a distributed graph architecture | Wei Han, Shuangcheng Li, Yawen Zhang, Heng Liu, Dimin Niu | 2023-08-15 |
| 11704271 | Scalable system-in-package architectures | Lide Duan, Wei Han, Yuhao Wang, Fei Xue, Yuanwei Fang | 2023-07-18 |
| 11681451 | HBM based memory lookup engine for deep learning accelerator | Peng Gu, Krishna T. Malladi | 2023-06-20 |
| 11658168 | Flash memory with improved bandwidth | Fei Xue, Shuangchen Li, Dimin Niu | 2023-05-23 |
| 11625341 | Narrow DRAM channel systems and methods | Jilan LIN, Dimin Niu, Shuangchen Li, Yuan Xie | 2023-04-11 |
| 11625296 | DRAM assist error correction mechanism for DDR SDRAM interface | Dimin Niu, Mu-Tien Chang, Hyun-Joong Kim, Won-Hyung Song, Jangseok Choi | 2023-04-11 |
| 11604744 | Dual-modal memory interface controller | Yuhao Wang, Wei Han, Dimin Niu, Lide Duan, Shuangchen Li +1 more | 2023-03-14 |
| 11568920 | Dual row-column major dram | Mu-Tien Chang, Dimin Niu | 2023-01-31 |
| 11556476 | ISA extension for high-bandwidth memory | Mu-Tien Chang, Krishna T. Malladi, Dimin Niu | 2023-01-17 |
| 11544189 | System and method for memory management | Jilan LIN, Shuangchen Li, Dimin Niu | 2023-01-03 |
| 11537531 | Cache memory that supports tagless addressing | Trung Diep | 2022-12-27 |
| 11513965 | Bandwidth boosted stacked memory | Krishna T. Malladi, Mu-Tien Chang, Dimin Niu | 2022-11-29 |
| 11500781 | Methods and apparatuses for addressing memory caches | Trung Diep | 2022-11-15 |
| 11487676 | Address mapping in memory systems | James Tringali | 2022-11-01 |
| 11475102 | Adaptive matrix multiplication accelerator for machine learning and deep learning applications | Dongyan Jiang, Dimin Niu | 2022-10-18 |
| 11437337 | Using electrical connections that traverse scribe lines to connect devices on a chip | Shuangchen Li, Wei Han, Dimin Niu, Yuhao Wang | 2022-09-06 |
| 11436165 | High bandwidth memory system | Krishna T. Malladi, Dimin Niu | 2022-09-06 |
| 11409839 | Programmable and hierarchical control of execution of GEMM operation on accelerator | Yuhao Wang, Fei Sun, Fei Xue, Yen-Kuang Chen | 2022-08-09 |
| 11409684 | Processing accelerator architectures | Jilan LIN, Dimin Niu, Shuangchen Li, Yuan Xie | 2022-08-09 |
| 11409672 | Unsuccessful write retry buffer | Brent Haukness | 2022-08-09 |
| 11398453 | HBM silicon photonic TSV architecture for lookup computing AI accelerator | Peng Gu, Krishna T. Malladi | 2022-07-26 |