Issued Patents All Time
Showing 1–25 of 34 patents
| Patent # | Title | Co-Inventors | Date |
|---|---|---|---|
| 12346286 | Two-dimensional processing array with a vertically stacked memory tile array | Zhe Zhang, Dimin Niu, Hongzhong Zheng | 2025-07-01 |
| 12346797 | Programmable access engine architecture for graph neural network and graph application | Heng Liu, Tianchan GUAN, Hongzhong Zheng | 2025-07-01 |
| 12340101 | Scaling out architecture for dram-based processing unit (DPU) | Dimin Niu, Bob Brennan, Krishna T. Malladi, Hongzhong Zheng | 2025-06-24 |
| 12332828 | Graph acceleration solution with cloud FPGA | Dimin Niu, Hongzhong Zheng, Zhe Zhang, Yuhao Wang | 2025-06-17 |
| 12216537 | Error detection, prediction and handling techniques for system-in-package memory architectures | Dimin Niu, Tianchan GUAN, Hongzhong Zheng | 2025-02-04 |
| 12210768 | Flexible memory extension systems and methods | Dimin Niu, Yijin GUAN, Shengcheng Wang, Yuhao Wang, Hongzhong Zheng | 2025-01-28 |
| 12189539 | Data processing system and memory management method of data processing system | Dimin Niu, Yijin GUAN, Tianchan GUAN, Hongzhong Zheng | 2025-01-07 |
| 12147474 | System for graph node sampling and method implemented by computer | Tianchan GUAN, Dimin Niu, Honzhong Zheng | 2024-11-19 |
| 12142338 | Memory priming and initialization systems and methods | Dimin Niu, Tianchan GUAN, Hongzhong Zheng | 2024-11-12 |
| 12073490 | Processing system that increases the capacity of a very fast memory | Yuhao Wang, Dimin Niu, Yijin GUAN, Shengcheng Wang, Hongzhong Zheng | 2024-08-27 |
| 12014057 | Data processing system | Dimin Niu, Tianchan GUAN, Yijin GUAN, Hongzhong Zheng | 2024-06-18 |
| 11954093 | Performing a top-k function using a binary heap tree | Fei Sun, Dimin Niu, Fei Xue, Yuanwei Fang | 2024-04-09 |
| 11934669 | Scaling out architecture for DRAM-based processing unit (DPU) | Dimin Niu, Bob Brennan, Krishna T. Malladi, Hongzhong Zheng | 2024-03-19 |
| 11900239 | Systems and methods for accelerating sparse neural network execution | Zhenyu Gu, Liu Liu, Yuan Xie | 2024-02-13 |
| 11886352 | Access friendly memory architecture of graph neural network sampling | Heng Liu, Tianchan GUAN, Hongzhong Zheng | 2024-01-30 |
| 11847049 | Processing system that increases the memory capacity of a GPGPU | Yuhao Wang, Dimin Niu, Yijin GUAN, Shengcheng Wang, Hongzhong Zheng | 2023-12-19 |
| 11841799 | Graph neural network accelerator with attribute caching | Tianchan GUAN, Heng Liu, Hongzhong Zheng | 2023-12-12 |
| 11836188 | Devices and methods for accessing and retrieving data in a graph | Tianchan GUAN, Zhe Zhang, Heng Liu, Wei Han, Dimin Niu +1 more | 2023-12-05 |
| 11762776 | Cache access method and associated graph neural network system | Zhe Zhang, Hongzhong Zheng | 2023-09-19 |
| 11662981 | Low-power programmable truncated multiplication circuitry | Wei Han, Fei Sun | 2023-05-30 |
| 11658168 | Flash memory with improved bandwidth | Fei Xue, Dimin Niu, Hongzhong Zheng | 2023-05-23 |
| 11625341 | Narrow DRAM channel systems and methods | Jilan LIN, Dimin Niu, Hongzhong Zheng, Yuan Xie | 2023-04-11 |
| 11604744 | Dual-modal memory interface controller | Yuhao Wang, Wei Han, Dimin Niu, Lide Duan, Fei Xue +1 more | 2023-03-14 |
| 11544189 | System and method for memory management | Jilan LIN, Dimin Niu, Hongzhong Zheng | 2023-01-03 |
| 11437337 | Using electrical connections that traverse scribe lines to connect devices on a chip | Wei Han, Dimin Niu, Yuhao Wang, Hongzhong Zheng | 2022-09-06 |