Issued Patents All Time
Showing 25 most recent of 27 patents
| Patent # | Title | Co-Inventors | Date |
|---|---|---|---|
| 12222871 | Methods and apparatuses for addressing memory caches | Hongzhong Zheng | 2025-02-11 |
| 12124382 | Cache memory that supports tagless addressing | Hongzhong Zheng | 2024-10-22 |
| 11921642 | Methods and apparatuses for addressing memory caches | Hongzhong Zheng | 2024-03-05 |
| 11537531 | Cache memory that supports tagless addressing | Hongzhong Zheng | 2022-12-27 |
| 11500781 | Methods and apparatuses for addressing memory caches | Hongzhong Zheng | 2022-11-15 |
| 11176037 | Wear leveling in a memory system | John Eric Linstadt | 2021-11-16 |
| 10891241 | Cache memory that supports tagless addressing | Hongzhong Zheng | 2021-01-12 |
| 10853261 | Methods and apparatuses for addressing memory caches | Hongzhong Zheng | 2020-12-01 |
| 10515010 | Wear leveling in a memory system | Eric Linstadt | 2019-12-24 |
| 10133676 | Cache memory that supports tagless addressing | Hongzhong Zheng | 2018-11-20 |
| 10102140 | Methods and apparatuses for addressing memory caches | Hongzhong Zheng | 2018-10-16 |
| 10037433 | Secure text retrieval | Pero Subasic | 2018-07-31 |
| 9934142 | Wear leveling in a memory system | Eric Linstadt | 2018-04-03 |
| 9734357 | Process authenticated memory page encryption | Pradeep Batra, Brian S. Leibowitz, Frederick A. Ware | 2017-08-15 |
| 9569359 | Methods and apparatuses for addressing memory caches | Hongzhong Zheng | 2017-02-14 |
| 9465961 | Methods and circuits for securing proprietary memory transactions | Frederick A. Ware, Brian S. Leibowitz, Pradeep Batra | 2016-10-11 |
| 9442838 | Remapping memory cells based on future endurance measurements | John Eric Linstadt, J. James Tringali, Hongzhong Zheng, Brent Haukness | 2016-09-13 |
| 9390025 | Wear leveling in a memory system | Eric Linstadt | 2016-07-12 |
| 9262342 | Process authenticated memory page encryption | Pradeep Batra, Brian S. Leibowitz, Frederick A. Ware | 2016-02-16 |
| 9069605 | Mechanism to schedule threads on OS-sequestered sequencers without operating system intervention | Richard Hankins, Hong Wang, Gautham Chinya, Shivnandan Kaushik, Bryant Bigbee +7 more | 2015-06-30 |
| 8935489 | Adaptively time-multiplexing memory references from multiple processor cores | Steven C. Woo, Michael Ching | 2015-01-13 |
| 8887174 | Mechanism for monitoring instruction set based thread execution on a plurality of instruction sequencers | Richard Hankins, Gautham Chinya, Hong Wang, Shivnandan Kaushik, Bryant Bigbee +7 more | 2014-11-11 |
| 8607235 | Mechanism to schedule threads on OS-sequestered sequencers without operating system intervention | Richard Hankins, Hong Wang, Gautham Chinya, Shivnandan Kaushik, Bryant Bigbee +7 more | 2013-12-10 |
| 8205200 | Compiler-based scheduling optimization hints for user-level threads | Shih-wei Liao, Ryan Rakvic, Richard Hankins, Hong Wang, Gansha Wu +6 more | 2012-06-19 |
| 8010969 | Mechanism for monitoring instruction set based thread execution on a plurality of instruction sequencers | Richard Hankins, Gautham Chinya, Hong Wang, Shivnandan Kaushik, Bryant Bigbee +7 more | 2011-08-30 |