Issued Patents All Time
Showing 26–50 of 207 patents
| Patent # | Title | Co-Inventors | Date |
|---|---|---|---|
| 12142338 | Memory priming and initialization systems and methods | Dimin Niu, Shuangchen Li, Tianchan GUAN | 2024-11-12 |
| 12141438 | Zero skipping techniques for reducing data movement | Fei Xue, Fei Sun, Yangjie ZHOU, Lide Duan | 2024-11-12 |
| 12141227 | Adaptive matrix multiplication accelerator for machine learning and deep learning applications | Dongyan Jiang, Dimin Niu | 2024-11-12 |
| 12124709 | Computing system and associated method | Tianchan GUAN, Yijin GUAN, Dimin Niu | 2024-10-22 |
| 12124382 | Cache memory that supports tagless addressing | Trung Diep | 2024-10-22 |
| 12099736 | Scalable architecture enabling large memory system for in-memory computations | Dongyan Jiang, Qiang Peng | 2024-09-24 |
| RE50130 | Computing system with adaptive back-up mechanism and method of operation thereof | Keith Chan, Wonseok Lee, Tackhwi Lee | 2024-09-17 |
| 12073490 | Processing system that increases the capacity of a very fast memory | Yuhao Wang, Dimin Niu, Yijin GUAN, Shengcheng Wang, Shuangchen Li | 2024-08-27 |
| 12056379 | HBM based memory lookup engine for deep learning accelerator | Peng Gu, Krishna T. Malladi | 2024-08-06 |
| 12056374 | Dynamic memory coherency biasing techniques | Lide Duan, Dimin Niu | 2024-08-06 |
| 12032828 | Coordinated in-module RAS features for synchronous DDR compatible memory | Mu-Tien Chang, Dimin Niu, Sun-Young Lim, Indong Kim, Jangseok Choi | 2024-07-09 |
| 12032497 | Scale-out high bandwidth memory system | Krishna T. Malladi, Dimin Niu, Peng Gu | 2024-07-09 |
| 12014057 | Data processing system | Dimin Niu, Tianchan GUAN, Yijin GUAN, Shuangchen Li | 2024-06-18 |
| 11947961 | Memory lookup computing mechanisms | Peng Gu, Krishna T. Malladi | 2024-04-02 |
| 11947471 | Unsuccessful write retry buffer | Brent Haukness | 2024-04-02 |
| 11940922 | ISA extension for high-bandwidth memory | Mu-Tien Chang, Krishna T. Malladi, Dimin Niu | 2024-03-26 |
| 11934669 | Scaling out architecture for DRAM-based processing unit (DPU) | Dimin Niu, Shuangchen Li, Bob Brennan, Krishna T. Malladi | 2024-03-19 |
| 11921656 | Heterogeneous accelerator for highly efficient learning systems | Krishna T. Malladi | 2024-03-05 |
| 11921642 | Methods and apparatuses for addressing memory caches | Trung Diep | 2024-03-05 |
| 11921638 | Flash-integrated high bandwidth memory appliance | Krishna T. Malladi | 2024-03-05 |
| 11893239 | Quasi-synchronous protocol for large bandwidth memory systems | Krishna T. Malladi | 2024-02-06 |
| 11886352 | Access friendly memory architecture of graph neural network sampling | Heng Liu, Tianchan GUAN, Shuangchen Li | 2024-01-30 |
| 11847049 | Processing system that increases the memory capacity of a GPGPU | Yuhao Wang, Dimin Niu, Yijin GUAN, Shengcheng Wang, Shuangchen Li | 2023-12-19 |
| 11841799 | Graph neural network accelerator with attribute caching | Tianchan GUAN, Heng Liu, Shuangchen Li | 2023-12-12 |
| 11836188 | Devices and methods for accessing and retrieving data in a graph | Shuangchen Li, Tianchan GUAN, Zhe Zhang, Heng Liu, Wei Han +1 more | 2023-12-05 |