Issued Patents All Time
Showing 101–125 of 207 patents
| Patent # | Title | Co-Inventors | Date |
|---|---|---|---|
| 11079936 | 3-D stacked memory with reconfigurable compute logic | Mu-Tien Chang, Prasun Gera, Dimin Niu | 2021-08-03 |
| 11029879 | Page size synchronization and page size aware scheduling method for non-volatile memory dual in-line memory module (NVDIMM) over memory channel | Dimin Niu, Mu-Tien Chang, Sun-Young Lim, Jae Gon Lee, Indong Kim | 2021-06-08 |
| 11030088 | Pseudo main memory system | Krishna T. Malladi, Jongmin Gim | 2021-06-08 |
| 11010242 | DRAM assist error correction mechanism for DDR SDRAM interface | Dimin Niu, Mu-Tien Chang, Hyun-Joong Kim, Won-Hyung Song, Jangseok Choi | 2021-05-18 |
| 10977118 | DRAM assist error correction mechanism for DDR SDRAM interface | Dimin Niu, Mu-Tien Chang, Hyun-Joong Kim, Won-Hyung Song, Jangseok Choi | 2021-04-13 |
| 10978134 | Method and device for refreshing memory | Dimin Niu, Shuangchen Li | 2021-04-13 |
| 10929026 | Multi-cell structure for non-volatile resistive memory | Dimin Niu, Mu-Tien Chang | 2021-02-23 |
| 10915451 | Bandwidth boosted stacked memory | Krishna T. Malladi, Mu-Tien Chang, Dimin Niu | 2021-02-09 |
| 10908820 | Host-based and client-based command scheduling in large bandwidth memory systems | Krishna T. Malladi, Robert Brennan | 2021-02-02 |
| 10908993 | Method to deliver in-DRAM ECC information through DDR bus | Dimin Niu, Mu-Tien Chang, Hyun-Joong Kim, Won-Hyung Song, Jangseok Choi | 2021-02-02 |
| 10891241 | Cache memory that supports tagless addressing | Trung Diep | 2021-01-12 |
| 10866900 | ISA extension for high-bandwidth memory | Mu-Tien Chang, Krishna T. Malladi, Dimin Niu | 2020-12-15 |
| 10866897 | Byte-addressable flash-based memory module with prefetch mode that is adjusted based on feedback from prefetch accuracy that is calculated by comparing first decoded address and second decoded address, where the first decoded address is sent to memory controller, and the second decoded address is sent to prefetch buffer | Mu-Tien Chang, Dimin Niu, Dongyan Jiang | 2020-12-15 |
| 10853265 | Address mapping in memory systems | James Tringali | 2020-12-01 |
| 10853261 | Methods and apparatuses for addressing memory caches | Trung Diep | 2020-12-01 |
| 10824499 | Memory system architectures using a separate system control path or channel for processing error information | Chaohong Hu, Uksong Kang, Zhan Ping | 2020-11-03 |
| 10810144 | System and method for operating a DRR-compatible asynchronous memory module | Sun-Young Lim, Mu-Tien Chang, Dimin Niu, Indong Kim | 2020-10-20 |
| 10795764 | Method to deliver in-DRAM ECC information through DDR bus | Dimin Niu, Mu-Tien Chang, Hyun-Joong Kim, Won-Hyung Song, Jangseok Choi | 2020-10-06 |
| 10762000 | Techniques to reduce read-modify-write overhead in hybrid DRAM/NAND memory | Mu-Tien Chang, Heehyun Nam, Youngsik Kim, Youngjin Cho, Dimin Niu | 2020-09-01 |
| 10732866 | Scaling out architecture for DRAM-based processing unit (DPU) | Dimin Niu, Shuangchen Li, Bob Brennan, Krishna T. Malladi | 2020-08-04 |
| 10732929 | Computing accelerator using a lookup table | Krishna T. Malladi, Peng Gu, Robert Brennan | 2020-08-04 |
| 10705969 | Dedupe DRAM cache | Mu-Tien Chang, Andrew Chang, Dongyan Jiang | 2020-07-07 |
| 10705988 | Memory module threading with staggered data transfers | Frederick A. Ware | 2020-07-07 |
| 10684823 | Unsuccessful write retry buffer | Brent Haukness | 2020-06-16 |
| 10678704 | Method and apparatus for enabling larger memory capacity than physical memory size | Dongyan Jiang, Changhui Lin, Krishna T. Malladi, Jongmin Gim | 2020-06-09 |