Issued Patents All Time
Showing 151–175 of 207 patents
| Patent # | Title | Co-Inventors | Date |
|---|---|---|---|
| 10282294 | Mitigating DRAM cache metadata access overhead with SRAM metadata cache and bloom filter | Mu-Tien Chang, Dimin Niu | 2019-05-07 |
| 10282436 | Memory apparatus for in-place regular expression search | Krishna T. Malladi | 2019-05-07 |
| 10268413 | Overflow region memory management | Dongyan Jiang, Changhui Lin, Krishna T. Malladi, Jongmin Gim | 2019-04-23 |
| 10268607 | Memory module threading with staggered data transfers | Frederick A. Ware | 2019-04-23 |
| 10268541 | DRAM assist error correction mechanism for DDR SDRAM interface | Dimin Niu, Mu-Tien Chang, Hyun-Joong Kim, Won-Hyung Song, Jangseok Choi | 2019-04-23 |
| 10261897 | Tail latency aware foreground garbage collection algorithm | Jongmin Gim | 2019-04-16 |
| 10242728 | DPU architecture | Shaungchen Li, Dimin Niu, Krishna T. Malladi | 2019-03-26 |
| 10223252 | Hybrid DRAM array including dissimilar memory cells | Mu-Tien Chang, Dimin Niu | 2019-03-05 |
| 10180808 | Software stack and programming for DPU operations | Shaungchen Li, Dimin Niu, Krishna T. Malladi | 2019-01-15 |
| 10180906 | HBM with in-memory cache manager | Tyler Stocksdale, Mu-Tien Chang | 2019-01-15 |
| 10169124 | Unified object interface for memory and storage system | Rakesh Ramesh, Krishna T. Malladi | 2019-01-01 |
| 10162554 | System and method for controlling a programmable deduplication ratio for a memory system | Krishna T. Malladi, Dimin Niu | 2018-12-25 |
| 10157657 | Selective refresh with software components | James Tringali, Frederick A. Ware | 2018-12-18 |
| 10133676 | Cache memory that supports tagless addressing | Trung Diep | 2018-11-20 |
| 10114560 | Hybrid memory controller with command buffer for arbitrating access to volatile and non-volatile memories in a hybrid memory group | Dimin Niu, Mu-Tien Chang, Sun-Young Lim, Indong Kim | 2018-10-30 |
| 10101935 | System and method for providing expandable and contractible memory overprovisioning | Krishna T. Malladi | 2018-10-16 |
| 10102140 | Methods and apparatuses for addressing memory caches | Trung Diep | 2018-10-16 |
| 10073790 | Electronic system with memory management mechanism and method of operation thereof | Krishna T. Malladi | 2018-09-11 |
| 10049717 | Wear leveling for storage or memory device | Dimin Niu, Mu-Tien Chang, Kyung-Chang Ryoo | 2018-08-14 |
| 10013212 | System architecture with memory channel DRAM FPGA module | Mu-Tien Chang | 2018-07-03 |
| 10002044 | Memory devices and modules | Chaohong Hu, Uksong Kang, Zhan Ping | 2018-06-19 |
| 10002043 | Memory devices and modules | Chaohong Hu, Liang Yin, Uksong Kang | 2018-06-19 |
| 9996390 | Method and system for performing adaptive context switching | Suhas | 2018-06-12 |
| 9983821 | Optimized hopscotch multiple hash tables for efficient memory in-line deduplication application | Frederic Sala, Chaohong Hu, Dimin Niu, Mu-Tien Chang | 2018-05-29 |
| 9971511 | Hybrid memory module and transaction-based memory interface | Dimin Niu, Mu-Tien Chang | 2018-05-15 |