Issued Patents All Time
Showing 201–225 of 739 patents
| Patent # | Title | Co-Inventors | Date |
|---|---|---|---|
| 11308009 | Interface for memory readout from a memory component in the event of fault | Kenneth L. Wright | 2022-04-19 |
| 11307243 | Memory controller with integrated test circuitry | — | 2022-04-19 |
| 11302367 | Area-efficient, width-adjustable signaling interface | — | 2022-04-12 |
| 11301378 | Nonvolatile physical memory with DRAM cache and mapping thereof | John Eric Linstadt, Christopher Haywood | 2022-04-12 |
| 11276440 | Memory controllers, systems, and methods supporting multiple request modes | Richard E. Perego | 2022-03-15 |
| 11270741 | Deferred fractional memory row activation | James E. Harris, Thomas Vogelsang, Ian Shaeffer | 2022-03-08 |
| 11264085 | Memory component for deployment in a dynamic stripe width memory system | John Eric Linstadt, Kenneth L. Wright | 2022-03-01 |
| 11258522 | Periodic calibration for communication channels by drift tracking | Craig E. Hampel, Richard E. Perego | 2022-02-22 |
| 11257544 | Fast read speed memory device | Deepak C. Sekar, Gary B. Bronner | 2022-02-22 |
| 11257539 | Reduced transport energy in a memory system | John Eric Linstadt, Thomas Vogelsang | 2022-02-22 |
| 11256613 | Memory system with activate-leveling method | Craig E. Hampel | 2022-02-22 |
| 11250901 | Protocol for memory power-mode control | Wayne F. Ellis, Wayne S. Richardson, Akash Bansal, Lawrence Lai, Kishore Ven Kasamsetty | 2022-02-15 |
| 11249845 | Error-correction-detection coding for hybrid memory module | — | 2022-02-15 |
| 11249649 | Memory system with threaded transaction support | Ely Tsern | 2022-02-15 |
| 11243897 | High capacity memory system with improved command-address and chip-select signaling mode | Abhijit M. Abhyankar, Suresh Rajan | 2022-02-08 |
| 11226909 | DRAM interface mode with interruptible internal transfer operation | Liji Gopalakrishnan, Brent Haukness | 2022-01-18 |
| 11210242 | Memory system with cached memory module operations | Kenneth L. Wright, John Eric Linstadt, Craig E. Hampel | 2021-12-28 |
| 11211114 | Memories and memory components with interconnected and redundant data interfaces | Ely Tsern, John Eric Linstadt, Thomas J. Giovannini, Scott C. Best, Kenneth L. Wright | 2021-12-28 |
| 11204825 | Memory device and repair method with column-based error code tracking | Brent Haukness | 2021-12-21 |
| 11194749 | Cross-threaded memory system | Kishore Ven Kasamsetty | 2021-12-07 |
| 11194585 | Multiplier-accumulator circuitry having processing pipelines and methods of operating same | Cheng C. Wang | 2021-12-07 |
| 11194509 | High capacity, high performance memory system | — | 2021-12-07 |
| 11195570 | Low-power source-synchronous signaling | Jared L. Zerbe | 2021-12-07 |
| 11170842 | Stacked semiconductor device | — | 2021-11-09 |
| 11164622 | Variable width memory module supporting enhanced error detection and correction | John Eric Linstadt, Kenneth L. Wright | 2021-11-02 |