Issued Patents All Time
Showing 151–175 of 739 patents
| Patent # | Title | Co-Inventors | Date |
|---|---|---|---|
| 11600310 | Area-efficient, width-adjustable signaling interface | — | 2023-03-07 |
| 11573897 | Hybrid memory module | — | 2023-02-07 |
| 11573849 | Memory module register access | Thomas J. Giovannini, Catherine Chen, Scott C. Best, John Eric Linstadt | 2023-02-07 |
| 11568919 | High capacity memory system using standard controller component | Suresh Rajan, Scott C. Best | 2023-01-31 |
| 11567120 | Memory controller with integrated test circuitry | — | 2023-01-31 |
| 11562778 | Memory module and system supporting parallel and serial access modes | Scott C. Best, William N. Ng | 2023-01-24 |
| 11556164 | Memory IC with data loopback | Robert E. Palmer, John W. Poulton, Andrew M. Fuller | 2023-01-17 |
| 11556433 | High performance persistent memory | J. James Tringali, Ely Tsern | 2023-01-17 |
| 11551735 | High performance, non-volatile memory module | Ely Tsern, John Eric Linstadt | 2023-01-10 |
| 11552748 | Communication channel calibration for drift conditions | Richard E. Perego, Craig E. Hampel | 2023-01-10 |
| 11551741 | Protocol for refresh between a memory controller and a memory device | Brent Haukness | 2023-01-10 |
| 11533077 | Pseudo-differential signaling for modified single-ended interface | Carl W. Werner | 2022-12-20 |
| 11507280 | Maintenance operations in a DRAM | Robert E. Palmer, John W. Poulton | 2022-11-22 |
| 11502681 | Method and system for balancing power-supply loading | Talip Ucar | 2022-11-15 |
| 11487617 | Memory component with error-detect-correct code interface | Brent Haukness, Lawrence Lai | 2022-11-01 |
| 11487679 | Semiconductor memory systems with on-die data buffering | Amir Amirkhany, Suresh Rajan, Mohammad Hekmat, Dinesh Patil | 2022-11-01 |
| 11481192 | Dual-domain combinational logic circuitry | John Eric Linstadt | 2022-10-25 |
| 11474959 | Memory module with reduced read/write turnaround overhead | Craig E. Hampel | 2022-10-18 |
| 11474957 | Memory access during memory calibration | Ian Shaeffer | 2022-10-18 |
| 11474590 | Dynamically changing data access bandwidth by selectively enabling and disabling data links | — | 2022-10-18 |
| 11468925 | DRAM interface mode with improved channel integrity and efficiency at high signaling rates | — | 2022-10-11 |
| 11467986 | Memory controller for selective rank or subrank access | Craig E. Hampel | 2022-10-11 |
| 11455368 | MAC processing pipeline having conversion circuitry, and methods of operating same | Cheng C. Wang | 2022-09-27 |
| 11456025 | Hybrid memory module | John Eric Linstadt, Kenneth L. Wright | 2022-09-27 |
| 11450356 | Synchronous signaling interface with over-clocked timing reference | John Eric Linstadt, Carl W. Werner | 2022-09-20 |