Issued Patents All Time
Showing 51–75 of 739 patents
| Patent # | Title | Co-Inventors | Date |
|---|---|---|---|
| 12094565 | Memory component with adjustable core-to-interface data rate ratio | Ely Tsern | 2024-09-17 |
| 12086039 | High performance persistent memory | J. James Tringali, Ely Tsern | 2024-09-10 |
| 12079135 | Techniques for storing data and tags in different memory arrays | — | 2024-09-03 |
| 12072807 | Storage and access of data and tags in a multi-way set associative cache | Thomas Vogelsang, Michael Raymond Miller, Collins Williams | 2024-08-27 |
| 12072802 | Hybrid memory module | — | 2024-08-27 |
| 12066957 | Interface for memory readout from a memory component in the event of fault | Kenneth L. Wright | 2024-08-20 |
| 12050513 | Energy-efficient error-correction-detection storage | John Eric Linstadt, Liji Gopalakrishnan | 2024-07-30 |
| 12032845 | Memory controller partitioning for hybrid memory system | John Eric Linstadt | 2024-07-09 |
| 12026038 | Memory controller with error detection and retry modes of operation | Ely Tsern, Mark A. Horowitz | 2024-07-02 |
| 12015428 | MAC processing pipeline using filter weights having enhanced dynamic range, and methods of operating same | Cheng C. Wang | 2024-06-18 |
| 12014089 | High capacity, high performance memory system | — | 2024-06-18 |
| 12008066 | Mac processing pipeline having conversion circuitry, and methods of operating same | Cheng C. Wang | 2024-06-11 |
| 12002532 | Command/address channel error detection | John Eric Linstadt | 2024-06-04 |
| 11996160 | Low power signaling interface | John Eric Linstadt, Carl W. Werner | 2024-05-28 |
| 11994930 | Optimizing power in a memory device | Dinesh Patil, Amir Amirkhany, Farrukh Aquil, Kambiz Kaviani | 2024-05-28 |
| 11990912 | Data transmission using delayed timing signals | Ely Tsern, Brian S. Leibowitz, Jared L. Zerbe | 2024-05-21 |
| 11984163 | Processing unit with fast read speed memory device | Deepak C. Sekar, Gary B. Bronner | 2024-05-14 |
| 11983137 | Memory system with independently adjustable core and interface data rates | — | 2024-05-14 |
| 11967364 | Variable width memory module supporting enhanced error detection and correction | John Eric Linstadt, Kenneth L. Wright | 2024-04-23 |
| 11963299 | Load reduced memory module | Suresh Rajan | 2024-04-16 |
| 11960886 | Multiplier-accumulator processing pipelines and processing component, and methods of operating same | Cheng C. Wang, Valentin Ossman | 2024-04-16 |
| 11960856 | Multiplier-accumulator processing pipeline using filter weights having gaussian floating point data format | — | 2024-04-16 |
| 11960418 | Semiconductor memory systems with on-die data buffering | Amir Amirkhany, Suresh Rajan, Mohammad Hekmat, Dinesh Patil | 2024-04-16 |
| 11960344 | Memory controller with looped-back calibration data receiver | Robert E. Palmer, John W. Poulton, Andrew M. Fuller | 2024-04-16 |
| 11953981 | Memory module register access | Thomas J. Giovannini, Catherine Chen, Scott C. Best, John Eric Linstadt | 2024-04-09 |